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Tsirkin" , Marcel Apfelbaum Subject: [PATCH v1 05/23] q35: Fix incorrect values for PCIEXBAR masks Date: Tue, 20 Jun 2023 13:24:39 -0400 Message-Id: <8e756802c5ffd314051fe8be79c021a387ae0158.1687278381.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::112d; envelope-from=jupham125@gmail.com; helo=mail-yw1-x112d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 20 Jun 2023 15:45:55 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1687290367807100001 Content-Type: text/plain; charset="utf-8" There are two small issues in PCIEXBAR address mask handling: - wrong bit positions for address mask bits (see PCIEXBAR description in Q35 datasheet) - incorrect usage of 64ADR_MASK Due to this, attempting to write a valid PCIEXBAR address may cause it to shift to another address, causing memory layout corruption where emulated MMIO regions may overlap real (passed through) MMIO ranges. Fix this by providing correct values. I included the xen_enabled() check as I did not want to impact current use cases that are not xen related (if they are not seeing a problem). Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- hw/pci-host/q35.c | 16 +++++++++++++--- include/hw/pci-host/q35.h | 4 ++-- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index fe5fc0f47c..1fe4e5a5c9 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -37,6 +37,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/module.h" +#include "sysemu/xen.h" =20 /*************************************************************************= *** * Q35 host @@ -324,12 +325,21 @@ static void mch_update_pciexbar(MCHPCIState *mch) break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: length =3D 128 * 1024 * 1024; - addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | - MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; + if (!xen_enabled()) { + addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | + MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; + } else { + addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK; + } break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: length =3D 64 * 1024 * 1024; - addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; + if (!xen_enabled()) { + addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; + } else { + addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK | + MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK; + } break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: qemu_log_mask(LOG_GUEST_ERROR, "Q35: Reserved PCIEXBAR LENGTH\n"); diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index e89329c51e..441cce6ccd 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -105,8 +105,8 @@ struct Q35PCIHost { #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) -#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) -#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) +#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 27)) +#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 26)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1)) --=20 2.34.1