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[147.192.9.144]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-823187716ebsm8661487b3a.66.2026.01.25.23.04.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jan 2026 23:04:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769411057; x=1770015857; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8FW3Xgb6O5qaPdMbHJGW4nylfvciL9bC4hS3dP0yYtQ=; b=Z45nBW7SuEg2aHYl8HU56leVOpybdQef32/aB0XpkWqJMNKEL3vU+LoU3oIclhkX2M RanX1Guj75U/absj0FnG9ST0j9hmcQTqYiWsh4fH3bilvSnZRiC7zbpP2YiFQj+i8qdZ BuzHsJejQCXQe0C7kZrp7F7HLjCIL8EXsDW4SzNow9uDiX5BknKXI8HTr4uf5toNjr1S 7bqa+hwxpvTw1odOn3rvPZ7TlXxI54H959SheonBvUWWtPDEF1MuyxpCQbUdoVUl6Ubp vMNrLZVmijOS/xouJXGOv1Op7H7tgI5zq7vXEOCJdhVSVWmSUcXHy/MpQ4G7MrKNmVYt AOqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769411057; x=1770015857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8FW3Xgb6O5qaPdMbHJGW4nylfvciL9bC4hS3dP0yYtQ=; b=hv2i3UKH/ob10IhG3Of94JgPw1wQuicpwAcmA5K1GUvT+Ig8D2CdIuFgEruUmIyV23 jVvWVUutncbexxuru9TYTubexD4htEF6CB189A4C6qHHXa4iD1l4Oy5zpinAEn/cADgb J1jDVuCgSlSVbWQHC8O3afp+nj2ro6eXYrkOcHoWEba/NYUSpgX89LxjoUdjjvraIIjc Drs7jQfxhik0HXtpBApvBNFlINrrpyMWJ3cS85bblZ1H4gPLxhy83OSp9GQOtrAX0+mo ZWQ5QouzmqjmfYKkWZKZRVkOCASlHj57Dr4G5xVDfIoCDIAGLQyqhF/dIjQICoW6abkL UwGA== X-Gm-Message-State: AOJu0YyKbxxKIn9VWRa+Mb22LgHerLuiQf6FzhdtieETJWtXdezxw70R scv7W8t+t0M/odao25+lHtMDW+2fCYPmDv7gnIM6iyy+Q4EZbFGEqK/mRb90gxtI X-Gm-Gg: AZuq6aIIE/cU9w0oxVZQYfWkHg/u6tkiYp3eJE6ycDpdI0nAlZwc9rWTjwPeIYh5nYc z5ThaAN2FPkl1CgTTAuCvhMoWGHKmOLFri2/ENJZL5xUNgW8nTbi5Kmskn67XntccqrU5bTsRK2 MFZMXIUyqxZ2/EkHEnrGxqdvPkkahVw7Du5i8OucIipMec9E3amw9F/wnaXgdtcHm7QocEicK8k yWzOZxuY2W1GN7UARYOIjVKqGTrPQRqKlcBXBmrT3VFPX2HM/gG//c2tOJtbDKf95sBjMtsmj2C vejVwJLA6E6IRUvUxUOLooLYFNrpYlu4lliMt9craiLete9bEd1lFtYPtSrHiL1X6BRxP7MtcyG uYV6ZS4S+uepCXZDOz6bgYZvMF3gj5UiQ24awtW6gpsHmfwDCS9KK7aWlDr9/gbhgQP0o+ueNYP 9pCj/IcXhPHuMoZOHFkqeGw6GC76G2jSzhMt+bMTJbeycSJJBrg4oI X-Received: by 2002:a05:6a00:3e11:b0:81f:3f88:89ee with SMTP id d2e1a72fcca58-823411b83c6mr3738378b3a.12.1769411056966; Sun, 25 Jan 2026 23:04:16 -0800 (PST) From: Kohei Tokunaga To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , WANG Xuerui , Aurelien Jarno , Huacai Chen , Jiaxun Yang , Aleksandar Rikalo , Palmer Dabbelt , Alistair Francis , Stefan Weil , Kohei Tokunaga , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Stefan Hajnoczi , Pierrick Bouvier Subject: [PATCH v4 02/33] tcg/wasm64: Add register-related definitions Date: Mon, 26 Jan 2026 07:03:15 +0000 Message-ID: <8cccaa9366173c874e08d909184bd1c1214a83aa.1769407033.git.ktokunaga.mail@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=ktokunaga.mail@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1769411602521158500 Content-Type: text/plain; charset="utf-8" This commit adds the register allocation definitions and register names to the Wasm backend. As in TCI, call arguments are stored on the stack buffer and the return value is placed in the registers R0 and R1 when needed. Signed-off-by: Kohei Tokunaga --- tcg/wasm64/tcg-target.c.inc | 77 +++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 tcg/wasm64/tcg-target.c.inc diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc new file mode 100644 index 0000000000..3affc17232 --- /dev/null +++ b/tcg/wasm64/tcg-target.c.inc @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2009, 2011 Stefan Weil + * + * Based on tci/tcg-target.c.inc + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +static const int tcg_target_reg_alloc_order[] =3D { + TCG_REG_R2, + TCG_REG_R3, + TCG_REG_R4, + TCG_REG_R5, + TCG_REG_R6, + TCG_REG_R7, + TCG_REG_R8, + TCG_REG_R9, + TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R12, + TCG_REG_R13, + TCG_REG_R14, + TCG_REG_R15, + /* 2 of these are call clobbered, so use them last. */ + TCG_REG_R1, + TCG_REG_R0, +}; + +#ifdef CONFIG_DEBUG_TCG +static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { + "r00", + "r01", + "r02", + "r03", + "r04", + "r05", + "r06", + "r07", + "r08", + "r09", + "r10", + "r11", + "r12", + "r13", + "r14", + "r15", +}; +#endif + +/* No call arguments via registers. All will be stored on the "stack". */ +static const int tcg_target_call_iarg_regs[] =3D { }; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot < 128 / TCG_TARGET_REG_BITS); + return TCG_REG_R0 + slot; +} --=20 2.43.0