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charset="utf-8" To handle the new Hypervisor CSR register aliasing let's use pointers. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 11 +++++++++-- target/riscv/cpu.h | 9 ++++++++- target/riscv/cpu_helper.c | 30 +++++++++++++++--------------- target/riscv/csr.c | 20 ++++++++++---------- target/riscv/op_helper.c | 14 +++++++------- 5 files changed, 49 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a07c5689b3..e61cf46a73 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -236,7 +236,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", *env->mstatus); if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatu= s); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vssta= tus); @@ -336,7 +336,7 @@ static void riscv_cpu_reset(CPUState *cs) mcc->parent_reset(cs); #ifndef CONFIG_USER_ONLY env->priv =3D PRV_M; - env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); + *env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause =3D 0; env->pc =3D env->resetvec; #endif @@ -465,8 +465,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); +#ifndef CONFIG_USER_ONLY + CPURISCVState *env =3D &cpu->env; +#endif =20 cpu_set_cpustate_pointers(cpu); + +#ifndef CONFIG_USER_ONLY + env->mstatus =3D &env->mstatus_novirt; +#endif } =20 static const VMStateDescription vmstate_riscv_cpu =3D { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 21ae5a8b19..9dc8303c62 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -122,7 +122,7 @@ struct CPURISCVState { target_ulong resetvec; =20 target_ulong mhartid; - target_ulong mstatus; + target_ulong *mstatus; =20 target_ulong mip; uint32_t miclaim; @@ -145,6 +145,13 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + /* The following registers are the "real" versions that the pointer + * versions point to. These should never be used unless you know what = you + * are doing. To access these use the pointer versions instead. This is + * required to handle the Hypervisor register swapping. + */ + target_ulong mstatus_novirt; + /* Hypervisor CSRs */ target_ulong hstatus; target_ulong hedeleg; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b00f66824a..9684da7f7d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -37,8 +37,8 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { - target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); - target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); + target_ulong mstatus_mie =3D get_field(*env->mstatus, MSTATUS_MIE); + target_ulong mstatus_sie =3D get_field(*env->mstatus, MSTATUS_SIE); target_ulong pending =3D env->mip & env->mie; target_ulong mie =3D env->priv < PRV_M || (env->priv =3D=3D PRV_M && m= status_mie); target_ulong sie =3D env->priv < PRV_S || (env->priv =3D=3D PRV_S && m= status_sie); @@ -75,7 +75,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) /* Return true is floating point support is currently enabled */ bool riscv_cpu_fp_enabled(CPURISCVState *env) { - if (env->mstatus & MSTATUS_FS) { + if (*env->mstatus & MSTATUS_FS) { return true; } =20 @@ -198,8 +198,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, int mode =3D mmu_idx; =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); + if (get_field(*env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(*env->mstatus, MSTATUS_MPP); } } =20 @@ -213,11 +213,11 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 hwaddr base; int levels, ptidxbits, ptesize, vm, sum; - int mxr =3D get_field(env->mstatus, MSTATUS_MXR); + int mxr =3D get_field(*env->mstatus, MSTATUS_MXR); =20 if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; - sum =3D get_field(env->mstatus, MSTATUS_SUM); + sum =3D get_field(*env->mstatus, MSTATUS_SUM); vm =3D get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: @@ -237,8 +237,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } } else { base =3D (hwaddr)(env->sptbr) << PGSHIFT; - sum =3D !get_field(env->mstatus, MSTATUS_PUM); - vm =3D get_field(env->mstatus, MSTATUS_VM); + sum =3D !get_field(*env->mstatus, MSTATUS_PUM); + vm =3D get_field(*env->mstatus, MSTATUS_VM); switch (vm) { case VM_1_09_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; @@ -492,8 +492,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx); =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); + if (get_field(*env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(*env->mstatus, MSTATUS_MPP); } } =20 @@ -599,12 +599,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (env->priv <=3D PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { /* handle the trap in S-mode */ - target_ulong s =3D env->mstatus; + target_ulong s =3D *env->mstatus; s =3D set_field(s, MSTATUS_SPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); - env->mstatus =3D s; + *env->mstatus =3D s; env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); env->sepc =3D env->pc; env->sbadaddr =3D tval; @@ -613,12 +613,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_mode(env, PRV_S); } else { /* handle the trap in M-mode */ - target_ulong s =3D env->mstatus; + target_ulong s =3D *env->mstatus; s =3D set_field(s, MSTATUS_MPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); - env->mstatus =3D s; + *env->mstatus =3D s; env->mcause =3D cause | ~(((target_ulong)-1) >> async); env->mepc =3D env->pc; env->mbadaddr =3D tval; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 74e911af08..a4b598d49a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -136,7 +136,7 @@ static int write_fflags(CPURISCVState *env, int csrno, = target_ulong val) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } - env->mstatus |=3D MSTATUS_FS; + *env->mstatus |=3D MSTATUS_FS; #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); return 0; @@ -159,7 +159,7 @@ static int write_frm(CPURISCVState *env, int csrno, tar= get_ulong val) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } - env->mstatus |=3D MSTATUS_FS; + *env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D val & (FSR_RD >> FSR_RD_SHIFT); return 0; @@ -183,7 +183,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } - env->mstatus |=3D MSTATUS_FS; + *env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); @@ -313,7 +313,7 @@ static int read_mhartid(CPURISCVState *env, int csrno, = target_ulong *val) /* Machine Trap Setup */ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mstatus; + *val =3D *env->mstatus; return 0; } =20 @@ -325,7 +325,7 @@ static int validate_vm(CPURISCVState *env, target_ulong= vm) =20 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong mstatus =3D env->mstatus; + target_ulong mstatus =3D *env->mstatus; target_ulong mask =3D 0; int dirty; =20 @@ -365,7 +365,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS)) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); - env->mstatus =3D mstatus; + *env->mstatus =3D mstatus; =20 return 0; } @@ -614,7 +614,7 @@ static int read_sstatus(CPURISCVState *env, int csrno, = target_ulong *val) { target_ulong mask =3D ((env->priv_ver >=3D PRIV_VERSION_1_10_0) ? sstatus_v1_10_mask : sstatus_v1_9_mask); - *val =3D env->mstatus & mask; + *val =3D *env->mstatus & mask; return 0; } =20 @@ -622,7 +622,7 @@ static int write_sstatus(CPURISCVState *env, int csrno,= target_ulong val) { target_ulong mask =3D ((env->priv_ver >=3D PRIV_VERSION_1_10_0) ? sstatus_v1_10_mask : sstatus_v1_9_mask); - target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); + target_ulong newval =3D (*env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } =20 @@ -737,7 +737,7 @@ static int read_satp(CPURISCVState *env, int csrno, tar= get_ulong *val) if (!riscv_feature(env, RISCV_FEATURE_MMU)) { *val =3D 0; } else if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { + if (env->priv =3D=3D PRV_S && get_field(*env->mstatus, MSTATUS_TVM= )) { return -1; } else { *val =3D env->satp; @@ -762,7 +762,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) validate_vm(env, get_field(val, SATP_MODE)) && ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { + if (env->priv =3D=3D PRV_S && get_field(*env->mstatus, MSTATUS_TVM= )) { return -1; } else { if((val ^ env->satp) & SATP_ASID) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 331cc36232..d150551bc9 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -83,11 +83,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) } =20 if (env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TSR)) { + get_field(*env->mstatus, MSTATUS_TSR)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - target_ulong mstatus =3D env->mstatus; + target_ulong mstatus =3D *env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_SPP); mstatus =3D set_field(mstatus, env->priv_ver >=3D PRIV_VERSION_1_10_0 ? @@ -96,7 +96,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong= cpu_pc_deb) mstatus =3D set_field(mstatus, MSTATUS_SPIE, 0); mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); - env->mstatus =3D mstatus; + *env->mstatus =3D mstatus; =20 return retpc; } @@ -112,7 +112,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - target_ulong mstatus =3D env->mstatus; + target_ulong mstatus =3D *env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); mstatus =3D set_field(mstatus, env->priv_ver >=3D PRIV_VERSION_1_10_0 ? @@ -121,7 +121,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) mstatus =3D set_field(mstatus, MSTATUS_MPIE, 0); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); - env->mstatus =3D mstatus; + *env->mstatus =3D mstatus; =20 return retpc; } @@ -132,7 +132,7 @@ void helper_wfi(CPURISCVState *env) =20 if (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TW)) { + get_field(*env->mstatus, MSTATUS_TW)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { cs->halted =3D 1; @@ -147,7 +147,7 @@ void helper_tlb_flush(CPURISCVState *env) if (!(env->priv >=3D PRV_S) || (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TVM))) { + get_field(*env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { tlb_flush(cs); --=20 2.24.0