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[91.157.170.157]) by smtp.gmail.com with ESMTPSA id v63sm1645409lje.39.2017.11.20.13.21.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Nov 2017 13:21:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DTF3+mU/xxZboCYV8UZ09Hb//OLojZa0AIzSAHN2Z40=; b=NtirAUpskCrarxY15kL2W7Kj07ubtIlxVMHs3n42Hbb9Vv4gtDaFZJ033eGVTWwRi2 sS8X/MNcoKZvQeS6DVQ3y5YfAnLvJ/Z5zm8DjDtJnsIKPN3qULHZmX9z3wAtk/csMzUG HlleUa8qiiBxJlvw00w7ZsKWfDSvsoE+si8vo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DTF3+mU/xxZboCYV8UZ09Hb//OLojZa0AIzSAHN2Z40=; b=fsIdDWJTAUAud3Mr9IGDez1AEw8gGLg5to1luvUPVRFllT078EXRa99z1ckJQ8v1Wc 2XMnocj6NoSwh55P7kHySzRdAu5wK5VFRc693sKZVb14j8yMfL/2GmDog2qwvuHOHHyc aQIMY+mwGJsYEGTqEsuO+g/J2GOe3M6qQL3oOJFav25NOaj2XvjMRNInEJKuYneuxoh9 72PK4TlzeJuWlxAUhZMNzx97pandIvZgyGcAWDiUJQeeafGF2/gkvGa1vWo3A3JYu314 UEFlGTirNqQJNEkMXAI8g0pf4dweYbH5hENOnmD2zU3e0vPij3dVaRPVpvS7/4JUwJPU WzsA== X-Gm-Message-State: AJaThX4zzb1BUo4O7B6X+yiCOgvFu8JRXKIiZ3bhW0/xJKf9kBXjoJba x4PNB7Yr9SFrPxSVlIlpZ5zm16bevR8= X-Google-Smtp-Source: AGs4zMZ4GWf0K0/5dprc0iX6T+Daq3/8fIwTzbIZQhFBp9DN5sF/hGLBkLrcXDo/Sv5rkTya3hlHew== X-Received: by 10.25.201.83 with SMTP id z80mr3079656lff.181.1511212917529; Mon, 20 Nov 2017 13:21:57 -0800 (PST) From: riku.voipio@linaro.org To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 23:21:36 +0200 Message-Id: <8bf8e9df4a7d82c7a47cc961c9cdee1615595de0.1511212753.git.riku.voipio@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PULL 08/15] linux-user/syscall.c: Handle SH4's exceptional alignment for p{read, write}64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Clarke Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: James Clarke Fixes: https://bugs.launchpad.net/qemu/+bug/1716767 Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-By: John Paul Adrian Glaubitz Signed-off-by: James Clarke Signed-off-by: Riku Voipio --- linux-user/syscall.c | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 8047bf3aac..9268c3ef69 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -671,18 +671,32 @@ static inline int next_free_host_timer(void) =20 /* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers= */ #ifdef TARGET_ARM -static inline int regpairs_aligned(void *cpu_env) { +static inline int regpairs_aligned(void *cpu_env, int num) +{ return ((((CPUARMState *)cpu_env)->eabi) =3D=3D 1) ; } #elif defined(TARGET_MIPS) && (TARGET_ABI_BITS =3D=3D 32) -static inline int regpairs_aligned(void *cpu_env) { return 1; } +static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } #elif defined(TARGET_PPC) && !defined(TARGET_PPC64) /* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pa= irs * of registers which translates to the same as ARM/MIPS, because we start= with * r3 as arg1 */ -static inline int regpairs_aligned(void *cpu_env) { return 1; } +static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } +#elif defined(TARGET_SH4) +/* SH4 doesn't align register pairs, except for p{read,write}64 */ +static inline int regpairs_aligned(void *cpu_env, int num) +{ + switch (num) { + case TARGET_NR_pread64: + case TARGET_NR_pwrite64: + return 1; + + default: + return 0; + } +} #else -static inline int regpairs_aligned(void *cpu_env) { return 0; } +static inline int regpairs_aligned(void *cpu_env, int num) { return 0; } #endif =20 #define ERRNO_TABLE_SIZE 1200 @@ -6870,7 +6884,7 @@ static inline abi_long target_truncate64(void *cpu_en= v, const char *arg1, abi_long arg3, abi_long arg4) { - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, TARGET_NR_truncate64)) { arg2 =3D arg3; arg3 =3D arg4; } @@ -6884,7 +6898,7 @@ static inline abi_long target_ftruncate64(void *cpu_e= nv, abi_long arg1, abi_long arg3, abi_long arg4) { - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, TARGET_NR_ftruncate64)) { arg2 =3D arg3; arg3 =3D arg4; } @@ -10508,7 +10522,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, #endif #ifdef TARGET_NR_pread64 case TARGET_NR_pread64: - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { arg4 =3D arg5; arg5 =3D arg6; } @@ -10518,7 +10532,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, unlock_user(p, arg2, ret); break; case TARGET_NR_pwrite64: - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { arg4 =3D arg5; arg5 =3D arg6; } @@ -11288,7 +11302,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, arg6 =3D ret; #else /* 6 args: fd, offset (high, low), len (high, low), advice */ - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { /* offset is in (3,4), len in (5,6) and advice in 7 */ arg2 =3D arg3; arg3 =3D arg4; @@ -11307,7 +11321,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, #ifdef TARGET_NR_fadvise64 case TARGET_NR_fadvise64: /* 5 args: fd, offset (high, low), len, advice */ - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { /* offset is in (3,4), len in 5 and advice in 6 */ arg2 =3D arg3; arg3 =3D arg4; @@ -11420,7 +11434,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, #ifdef TARGET_NR_readahead case TARGET_NR_readahead: #if TARGET_ABI_BITS =3D=3D 32 - if (regpairs_aligned(cpu_env)) { + if (regpairs_aligned(cpu_env, num)) { arg2 =3D arg3; arg3 =3D arg4; arg4 =3D arg5; --=20 2.14.2