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Tue, 03 Feb 2026 19:07:06 -0800 (PST) From: Fengyuan Yu <15fengyuan@gmail.com> To: Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Tao Tang Cc: Chao Liu , qemu-devel@nongnu.org, Fengyuan Yu <15fengyuan@gmail.com> Subject: [PATCH RFC v1 2/2] tests/qtest: Add Intel IOMMU bare-metal test Date: Wed, 4 Feb 2026 11:06:20 +0800 Message-Id: <89909ddad9c2b887056344bb93e5407e3639980d.1770172615.git.15fengyuan@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=15fengyuan@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 04 Feb 2026 02:17:23 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1770189576424154100 Content-Type: text/plain; charset="utf-8" Add a qtest suite for the Intel IOMMU (VT-d) device on the Q35 machine. The test exercises pass-through and translated translation modes using iommu-testdev and the qos-intel-iommu helpers. The test validates: - Root Entry Table and Context Entry Table configuration - 4-level page table walks for 48-bit address translation - Pass-through mode (identity mapping) - Translated mode with complete IOVA-to-PA translation - DMA transaction execution with memory content verification Signed-off-by: Fengyuan Yu <15fengyuan@gmail.com> --- tests/qtest/iommu-intel-test.c | 137 +++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 + 2 files changed, 139 insertions(+) create mode 100644 tests/qtest/iommu-intel-test.c diff --git a/tests/qtest/iommu-intel-test.c b/tests/qtest/iommu-intel-test.c new file mode 100644 index 0000000000..9f631be2c5 --- /dev/null +++ b/tests/qtest/iommu-intel-test.c @@ -0,0 +1,137 @@ +/* + * QTest for Intel IOMMU (VT-d) with iommu-testdev + * + * This QTest file is used to test the Intel IOMMU with iommu-testdev so t= hat + * we can test VT-d without any guest kernel or firmware. + * + * Copyright (c) 2026 Fengyuan Yu <15fengyuan@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqos/pci.h" +#include "libqos/pci-pc.h" +#include "hw/pci/pci_regs.h" +#include "hw/misc/iommu-testdev.h" +#include "libqos/qos-intel-iommu.h" + +#define DMA_LEN 4 + +/* Test configurations for different Intel IOMMU modes */ +static const QVTDTestConfig base_test_configs[] =3D { + { + .trans_mode =3D QVTD_TM_LEGACY_PT, + .dma_iova =3D 0x10100000, /* Use address in guest RAM range (insi= de 512MB) */ + .dma_pa =3D 0x10100000, + .dma_len =3D DMA_LEN, + .expected_result =3D 0, + .domain_id =3D 1, + }, + { + .trans_mode =3D QVTD_TM_LEGACY_TRANS, + .dma_iova =3D QVTD_TEST_IOVA, + .dma_pa =3D QVTD_TEST_PA, + .dma_len =3D DMA_LEN, + .expected_result =3D 0, + .domain_id =3D 1, + }, +}; + +static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QPCIBus **pcibu= s, + QPCIBar *bar) +{ + uint16_t vid, did; + QPCIDevice *dev =3D NULL; + int device_count =3D 0; + + *pcibus =3D qpci_new_pc(qts, NULL); + g_assert(*pcibus !=3D NULL); + + g_test_message("Scanning PCI bus for iommu-testdev (vendor:device =3D = 0x%04x:0x%04x)...", + IOMMU_TESTDEV_VENDOR_ID, IOMMU_TESTDEV_DEVICE_ID); + + /* Find device by vendor/device ID to avoid slot surprises. */ + for (int s =3D 0; s < 32 && !dev; s++) { + for (int fn =3D 0; fn < 8 && !dev; fn++) { + QPCIDevice *cand =3D qpci_device_find(*pcibus, QPCI_DEVFN(s, f= n)); + if (!cand) { + continue; + } + vid =3D qpci_config_readw(cand, PCI_VENDOR_ID); + did =3D qpci_config_readw(cand, PCI_DEVICE_ID); + + device_count++; + g_test_message(" Found PCI device at %02x:%x - vendor:device = =3D 0x%04x:0x%04x", + s, fn, vid, did); + + if (vid =3D=3D IOMMU_TESTDEV_VENDOR_ID && + did =3D=3D IOMMU_TESTDEV_DEVICE_ID) { + dev =3D cand; + g_test_message("Found iommu-testdev! devfn: 0x%x", cand->d= evfn); + } else { + g_free(cand); + } + } + } + + if (!dev) { + g_test_message("ERROR: iommu-testdev not found after scanning %d P= CI devices", device_count); + g_test_message("Expected vendor:device =3D 0x%04x:0x%04x (PCI_VEND= OR_ID_REDHAT:PCI_DEVICE_ID_REDHAT_TEST)", + IOMMU_TESTDEV_VENDOR_ID, IOMMU_TESTDEV_DEVICE_ID); + qpci_free_pc(*pcibus); + *pcibus =3D NULL; + g_test_skip("iommu-testdev not found on PCI bus - device may not b= e compiled or registered"); + return NULL; + } + + /* Enable device - iommu-testdev only uses MMIO, not I/O ports */ + uint16_t cmd =3D qpci_config_readw(dev, PCI_COMMAND); + cmd |=3D PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + qpci_config_writew(dev, PCI_COMMAND, cmd); + + *bar =3D qpci_iomap(dev, 0, NULL); + g_assert_false(bar->is_io); + + return dev; +} + +static void test_intel_iommu_translation(void) +{ + QTestState *qts; + QPCIBus *pcibus; + QPCIDevice *dev; + QPCIBar bar; + + /* Initialize QEMU environment for Intel IOMMU testing */ + qts =3D qtest_init("-machine q35,kernel-irqchip=3Dsplit " + "-accel tcg " + "-device intel-iommu,pt=3Don,aw-bits=3D48 " + "-device iommu-testdev,bus=3Dpcie.0,addr=3D0x4 " + "-m 512"); + + /* Setup and configure PCI device */ + dev =3D setup_qtest_pci_device(qts, &pcibus, &bar); + if (!dev) { + qtest_quit(qts); + return; + } + + /* Run the translation tests */ + g_test_message("### Starting Intel IOMMU translation tests...###"); + qvtd_translation_batch(base_test_configs, ARRAY_SIZE(base_test_configs= ), + qts, dev, bar, Q35_IOMMU_BASE); + g_test_message("### Intel IOMMU translation tests completed successful= ly! ###"); + + g_free(dev); + qpci_free_pc(pcibus); + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_func("/iommu-testdev/intel-translation", test_intel_iommu_tr= anslation); + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e2d2e68092..344e836300 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -95,6 +95,8 @@ qtests_i386 =3D \ (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] := []) + \ (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) = + \ (config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) += \ + (config_all_devices.has_key('CONFIG_VTD') and + config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') ? ['iommu-intel-test= '] : []) + \ (host_os !=3D 'windows' and = \ config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + = \ (config_all_devices.has_key('CONFIG_PCIE_PORT') and = \ --=20 2.39.5