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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3b1a2f75ca..4ea39d5641 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -903,14 +903,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt * no if hypervisor has delegated one of hs mode's interru= pt */ if (cause =3D=3D IRQ_VS_TIMER || cause =3D=3D IRQ_VS_SOFT = || - cause =3D=3D IRQ_VS_EXT) + cause =3D=3D IRQ_VS_EXT) { cause =3D cause - 1; - /* Trap to VS mode */ + } env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ --=20 2.26.2