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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775843865062154100 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point conversion instructions: - vconv_hf_h, vconv_h_hf, vconv_sf_w, vconv_w_sf: vconv operations - vcvt_hf_sf, vcvt_sf_hf: float <-> half float conversions - vcvt_hf_b, vcvt_hf_h, vcvt_hf_ub, vcvt_hf_uh: int to half float - vcvt_b_hf, vcvt_h_hf, vcvt_ub_hf, vcvt_uh_hf: half float to int Reviewed-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/mmvec/hvx_ieee_fp.h | 4 + target/hexagon/mmvec/hvx_ieee_fp.c | 18 ++++ target/hexagon/imported/mmvec/encode_ext.def | 18 ++++ target/hexagon/imported/mmvec/ext.idef | 97 ++++++++++++++++++++ 4 files changed, 137 insertions(+) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index dff2fab14c..bdc21e08f0 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -10,6 +10,7 @@ #include "fpu/softfloat.h" =20 #define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status) +#define f32_to_f16(A) float32_to_float16((A), true, &env->hvx_fp_status) =20 float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status); float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4, @@ -21,4 +22,7 @@ float32 qf_min_sf(float32 a1, float32 a2, float_status *f= p_status); float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status); float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status); =20 +int32_t conv_w_sf(float32 a, float_status *fp_status); +int16_t conv_h_hf(float16 a, float_status *fp_status); + #endif diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index 2ae79a485a..697f35b5ed 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -69,3 +69,21 @@ float16 qf_min_hf(float16 a1, float16 a2, float_status *= fp_status) } return float16_min(a1, a2, fp_status); } + +int32_t conv_w_sf(float32 a, float_status *fp_status) +{ + /* float32_to_int32 converts any NaN to MAX, hexagon looks at the sign= . */ + if (float32_is_any_nan(a)) { + return float32_is_neg(a) ? INT32_MIN : INT32_MAX; + } + return float32_to_int32_round_to_zero(a, fp_status); +} + +int16_t conv_h_hf(float16 a, float_status *fp_status) +{ + /* float16_to_int16 converts any NaN to MAX, hexagon looks at the sign= . */ + if (float16_is_any_nan(a)) { + return float16_is_neg(a) ? INT16_MIN : INT16_MAX; + } + return float16_to_int16_round_to_zero(a, fp_status); +} diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 72daf8724c..c1ed1b6c23 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -840,4 +840,22 @@ DEF_ENC(V6_vfneg_sf,"00011110--0-0110PP1uuuuu011ddddd") DEF_ENC(V6_vabs_hf,"00011110--0-0110PP1uuuuu100ddddd") DEF_ENC(V6_vabs_sf,"00011110--0-0110PP1uuuuu101ddddd") =20 +/* IEEE FP vcvt instructions */ +DEF_ENC(V6_vcvt_sf_hf,"00011110--0-0100PP1uuuuu100ddddd") +DEF_ENC(V6_vcvt_hf_sf,"00011111011vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vcvt_hf_ub,"00011110--0-0100PP1uuuuu001ddddd") +DEF_ENC(V6_vcvt_hf_b,"00011110--0-0100PP1uuuuu010ddddd") +DEF_ENC(V6_vcvt_hf_uh,"00011110--0-0100PP1uuuuu101ddddd") +DEF_ENC(V6_vcvt_hf_h,"00011110--0-0100PP1uuuuu111ddddd") +DEF_ENC(V6_vcvt_uh_hf,"00011110--0--101PP1uuuuu000ddddd") +DEF_ENC(V6_vcvt_h_hf,"00011110--0-0110PP1uuuuu000ddddd") +DEF_ENC(V6_vcvt_ub_hf,"00011111110vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vcvt_b_hf,"00011111110vvvvvPP1uuuuu110ddddd") + +/* IEEE FP vconv instructions */ +DEF_ENC(V6_vconv_sf_w,"00011110--0--101PP1uuuuu011ddddd") +DEF_ENC(V6_vconv_w_sf,"00011110--0--101PP1uuuuu001ddddd") +DEF_ENC(V6_vconv_hf_h,"00011110--0--101PP1uuuuu100ddddd") +DEF_ENC(V6_vconv_h_hf,"00011110--0--101PP1uuuuu010ddddd") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 1b16ed0628..788ce1d2ae 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -63,6 +63,9 @@ ITERATOR_INSN_ANY_SLOT_DOUBLE_VEC(WIDTH,TAG,SYNTAX2,DESCR= ,CODE) EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS), \ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 +#define ITERATOR_INSN_SHIFT_SLOT_FLT(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_HVX_FLT), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 #define ITERATOR_INSN_SHIFT3_SLOT(WIDTH,TAG,SYNTAX,DESCR,CODE) \ EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_CVI_VS_3SRC= ,A_NOTE_SHIFT_RESOURCE,A_NOTE_NOVP,A_NOTE_VA_UNARY), \ @@ -3046,6 +3049,100 @@ ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, "Vd3= 2.hf=3Dvabs(Vu32.hf)", \ ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, "Vd32.sf=3Dvabs(Vu32.sf)", \ "Vector IEEE abs: sf", VdV.sf[i] =3D float32_abs(VuV.sf[i])) =20 +/* Two pipes: P2 & P3, two outputs, 16-bit */ +#define ITERATOR_INSN_IEEE_FP_DOUBLE_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_16),= \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* Two pipes: P2 & P3, two outputs, 32-bit output */ +#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_= 32), \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* Single pipe, 16-bit output */ +#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16)= , \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* single pipe, output can feed 16- or 32-bit accumulate */ +#define ITERATOR_INSN_IEEE_FP_16_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16,= A_HVX_IEEE_FP_OUT_32), \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/*************************************************************************= ***** + * IEEE FP convert instructions + *************************************************************************= *****/ + +ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_ub, "Vdd32.hf=3Dvcvt(Vu32.ub)= ", + "Vector IEEE cvt from int: ub widen to hf", + VddV.v[0].hf[2*i] =3D uint64_to_float16_scalbn(VuV.ub[4*i], float_ro= und_nearest_even, 0); + VddV.v[0].hf[2*i+1] =3D uint64_to_float16_scalbn(VuV.ub[4*i+1], float_= round_nearest_even, 0); + VddV.v[1].hf[2*i] =3D uint64_to_float16_scalbn(VuV.ub[4*i+2], float_= round_nearest_even, 0); + VddV.v[1].hf[2*i+1] =3D uint64_to_float16_scalbn(VuV.ub[4*i+3], float_= round_nearest_even, 0)) + +ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_b, "Vdd32.hf=3Dvcvt(Vu32.b)", + "Vector IEEE cvt from int: b widen to hf", + VddV.v[0].hf[2*i] =3D int64_to_float16_scalbn(VuV.b[4*i], float_roun= d_nearest_even, 0); + VddV.v[0].hf[2*i+1] =3D int64_to_float16_scalbn(VuV.b[4*i+1], float_ro= und_nearest_even, 0); + VddV.v[1].hf[2*i] =3D int64_to_float16_scalbn(VuV.b[4*i+2], float_ro= und_nearest_even, 0); + VddV.v[1].hf[2*i+1] =3D int64_to_float16_scalbn(VuV.b[4*i+3], float_ro= und_nearest_even, 0)) + +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vcvt_sf_hf, "Vdd32.sf=3Dvcvt(Vu32.hf)", + "Vector IEEE cvt: hf widen to sf", + VddV.v[0].sf[i] =3D f16_to_f32(VuV.hf[2*i]); + VddV.v[1].sf[i] =3D f16_to_f32(VuV.hf[2*i+1])) + +ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_uh, "Vd32.hf=3Dvcvt(Vu32.uh)", + "Vector IEEE cvt from int: uh to hf", + VdV.hf[i] =3D uint64_to_float16_scalbn(VuV.uh[i], float_round_nearest_= even, 0)) +ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_h, "Vd32.hf=3Dvcvt(Vu32.h)", + "Vector IEEE cvt from int: h to hf", + VdV.hf[i] =3D int64_to_float16_scalbn(VuV.h[i], float_round_nearest_ev= en, 0)) +ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_uh_hf, "Vd32.uh=3Dvcvt(Vu32.hf)", + "Vector IEEE cvt to int: hf to uh", + VdV.uh[i] =3D float16_to_uint16_scalbn(VuV.hf[i], float_round_nearest_= even, 0, &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_h_hf, "Vd32.h=3Dvcvt(Vu32.hf)", + "Vector IEEE cvt to int: hf to h", + VdV.h[i] =3D float16_to_int16_scalbn(VuV.hf[i], float_round_nearest_e= ven, 0, &env->hvx_fp_status)) + +ITERATOR_INSN_IEEE_FP_16(32, vcvt_hf_sf, "Vd32.hf=3Dvcvt(Vu32.sf,Vv32.sf)", + "Vector IEEE cvt: sf to hf", + VdV.hf[2*i] =3D f32_to_f16(VuV.sf[i]); + VdV.hf[2*i+1] =3D f32_to_f16(VvV.sf[i])) + +ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_ub_hf, "Vd32.ub=3Dvcvt(Vu32.hf,Vv32.h= f)", "Vector cvt to int: hf narrow to ub", + VdV.ub[4*i] =3D float16_to_uint8_scalbn(VuV.hf[2*i], float_round_nea= rest_even, 0, &env->hvx_fp_status); + VdV.ub[4*i+1] =3D float16_to_uint8_scalbn(VuV.hf[2*i+1], float_round_n= earest_even, 0, &env->hvx_fp_status); + VdV.ub[4*i+2] =3D float16_to_uint8_scalbn(VvV.hf[2*i], float_round_nea= rest_even, 0, &env->hvx_fp_status); + VdV.ub[4*i+3] =3D float16_to_uint8_scalbn(VvV.hf[2*i+1], float_round_n= earest_even, 0, &env->hvx_fp_status)) + +ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_b_hf, "Vd32.b=3Dvcvt(Vu32.hf,Vv32.hf= )", + "Vector cvt to int: hf narrow to b", + VdV.b[4*i] =3D float16_to_int8_scalbn(VuV.hf[2*i], float_round_neare= st_even, 0, &env->hvx_fp_status); + VdV.b[4*i+1] =3D float16_to_int8_scalbn(VuV.hf[2*i+1], float_round_nea= rest_even, 0, &env->hvx_fp_status); + VdV.b[4*i+2] =3D float16_to_int8_scalbn(VvV.hf[2*i], float_round_neare= st_even, 0, &env->hvx_fp_status); + VdV.b[4*i+3] =3D float16_to_int8_scalbn(VvV.hf[2*i+1], float_round_nea= rest_even, 0, &env->hvx_fp_status)) + +ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_w_sf,"Vd32.w=3DVu32.sf", + "Vector conversion of sf32 format to int w", + VdV.w[i] =3D conv_w_sf(VuV.sf[i], &env->hvx_fp_status)) + +ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf,"Vd32.h=3DVu32.hf", + "Vector conversion of hf16 format to int hw", + VdV.h[i] =3D conv_h_hf(VuV.hf[i], &env->hvx_fp_status)) + +ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_sf_w,"Vd32.sf=3DVu32.w", + "Vector conversion of int w format to sf32", + VdV.sf[i] =3D int32_to_float32(VuV.w[i], &env->hvx_fp_status)) + +ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,"Vd32.hf=3DVu32.h", + "Vector conversion of int hw format to hf16", + VdV.hf[i] =3D float16_val(int16_to_float16(VuV.h[i], &env->hvx_fp_stat= us))) + /*************************************************************************= ***** DEBUG Vector/Register Printing *************************************************************************= *****/ --=20 2.37.2