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Mon, 19 May 2025 17:20:26 +0200 (CEST) Received: (qmail 1522 invoked by uid 990); 19 May 2025 15:20:25 -0000 Received: from unknown (HELO unkown) (::1) by skiff.uberspace.de (Haraka/3.0.1) with ESMTPSA; Mon, 19 May 2025 17:20:25 +0200 Authentication-Results: skiff.uberspace.de; auth=pass (plain) From: Julian Ganz To: qemu-devel@nongnu.org Cc: Julian Ganz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v5 13/25] target/mips: call plugin trap callbacks Date: Mon, 19 May 2025 17:19:53 +0200 Message-ID: <7e602c496a873fd55713eab740543683b69c98eb.1747666625.git.neither@nut.email> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Bar: ----- X-Rspamd-Report: REPLY(-4) BAYES_HAM(-2.999338) MID_CONTAINS_FROM(1) MIME_GOOD(-0.1) R_MISSING_CHARSET(0.5) X-Rspamd-Score: -5.599338 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nut.email; s=uberspace; h=from:to:cc:subject:date; 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helo=mailgate02.uberspace.is X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @nut.email) X-ZM-MESSAGEID: 1747668251652116600 Content-Type: text/plain; charset="utf-8" We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for MIPS targets. We consider the exceptions NMI and EXT_INTERRUPT to be asynchronous interrupts rather than exceptions. Signed-off-by: Julian Ganz Reviewed-by: Richard Henderson --- target/mips/tcg/system/tlb_helper.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index eccaf3624c..abc4d9fef0 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "qemu/bitops.h" +#include "qemu/plugin.h" =20 #include "cpu.h" #include "internal.h" @@ -1034,6 +1035,7 @@ void mips_cpu_do_interrupt(CPUState *cs) bool update_badinstr =3D 0; target_ulong offset; int cause =3D -1; + uint64_t last_pc =3D env->active_tc.PC; =20 if (qemu_loglevel_mask(CPU_LOG_INT) && cs->exception_index !=3D EXCP_EXT_INTERRUPT) { @@ -1052,6 +1054,7 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D EXCP_NONE; mips_semihosting(env); env->active_tc.PC +=3D env->error_code; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; case EXCP_DSS: env->CP0_Debug |=3D 1 << CP0DB_DSS; @@ -1336,6 +1339,14 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, env->CP0_DEPC); } + switch (cs->exception_index) { + case EXCP_NMI: + case EXCP_EXT_INTERRUPT: + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + break; + default: + qemu_plugin_vcpu_exception_cb(cs, last_pc); + } cs->exception_index =3D EXCP_NONE; } =20 --=20 2.49.0