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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Arpit Kumar , Jonathan Cameron , Fan Ni Subject: [PULL 25/33] hw/cxl: Physical Port Info FMAPI - update to current spec and add defines. Message-ID: <7df839591cf9354f7cc054ff6d01e16d46ff9f33.1771770471.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.798, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.79, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1771770894908154100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arpit Kumar Add a new cxl/cxl_ports.h header for field definitions related only to port commands. Bring field naming up to date with spec as 'version' bitmasks have been replaced with bitmasks of the specific features. Fix a small issue where a reserved value for USP was set to 2 rather than 0. Signed-off-by: Arpit Kumar Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Message-Id: <20260204173223.44122-2-Jonathan.Cameron@huawei.com> --- hw/cxl/cxl-mailbox-utils.c | 31 ++++++++++++++-------- include/hw/cxl/cxl_port.h | 53 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 11 deletions(-) create mode 100644 include/hw/cxl/cxl_port.h diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 2f449980cd..1c8cbe0f68 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -15,6 +15,7 @@ #include "hw/cxl/cxl.h" #include "hw/cxl/cxl_events.h" #include "hw/cxl/cxl_mailbox.h" +#include "hw/cxl/cxl_port.h" #include "hw/pci/pci.h" #include "hw/pci-bridge/cxl_upstream_port.h" #include "qemu/cutils.h" @@ -565,16 +566,16 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, } QEMU_PACKED *in; =20 /* - * CXL r3.1 Table 7-19: Get Physical Port State Port Information Block + * CXL r3.2 Table 7-19: Get Physical Port State Port Information Block * Format */ struct cxl_fmapi_port_state_info_block { uint8_t port_id; uint8_t config_state; - uint8_t connected_device_cxl_version; + uint8_t connected_device_mode; uint8_t rsv1; uint8_t connected_device_type; - uint8_t port_cxl_version_bitmask; + uint8_t supported_cxl_mode_bitmask; uint8_t max_link_width; uint8_t negotiated_link_width; uint8_t supported_link_speeds_vector; @@ -623,21 +624,30 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, if (port_dev) { /* DSP */ PCIDevice *ds_dev =3D pci_bridge_get_sec_bus(PCI_BRIDGE(port_d= ev)) ->devices[0]; - port->config_state =3D 3; + port->config_state =3D CXL_PORT_CONFIG_STATE_DSP; if (ds_dev) { if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { - port->connected_device_type =3D 5; /* Assume MLD for n= ow */ + /* Assume MLD for now */ + port->connected_device_type =3D + CXL_PORT_CONNECTED_DEV_TYPE_3_MLD; } else { - port->connected_device_type =3D 1; + port->connected_device_type =3D + CXL_PORT_CONNECTED_DEV_TYPE_PCIE; + port->connected_device_mode =3D + CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN; + } } else { - port->connected_device_type =3D 0; + port->connected_device_type =3D CXL_PORT_CONNECTED_DEV_TYP= E_NONE; + port->connected_device_mode =3D + CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN; } port->supported_ld_count =3D 3; } else if (usp->port =3D=3D in->ports[i]) { /* USP */ port_dev =3D PCI_DEVICE(usp); - port->config_state =3D 4; - port->connected_device_type =3D 0; + port->config_state =3D CXL_PORT_CONFIG_STATE_USP; + port->connected_device_type =3D 0; /* Reserved for USP */ + port->connected_device_mode =3D 0; /* Reserved for USP */ } else { return CXL_MBOX_INVALID_INPUT; } @@ -667,8 +677,7 @@ static CXLRetCode cmd_get_physical_port_state(const str= uct cxl_cmd *cmd, port->ltssm_state =3D 0x7; port->first_lane_num =3D 0; port->link_state =3D 0; - port->port_cxl_version_bitmask =3D 0x2; - port->connected_device_cxl_version =3D 0x2; + port->supported_cxl_mode_bitmask =3D CXL_PORT_SUPPORTS_68B_VH; } =20 pl_size =3D sizeof(*out) + sizeof(*out->ports) * in->num_ports; diff --git a/include/hw/cxl/cxl_port.h b/include/hw/cxl/cxl_port.h new file mode 100644 index 0000000000..04db60f7bc --- /dev/null +++ b/include/hw/cxl/cxl_port.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef CXL_PORT_H +#define CXL_PORT_H + +/* CXL r3.2 Table 7-19: Get Physical Port State Port Information Block For= mat */ +#define CXL_PORT_CONFIG_STATE_DISABLED 0x0 +#define CXL_PORT_CONFIG_STATE_BIND_IN_PROGRESS 0x1 +#define CXL_PORT_CONFIG_STATE_UNBIND_IN_PROGRESS 0x2 +#define CXL_PORT_CONFIG_STATE_DSP 0x3 +#define CXL_PORT_CONFIG_STATE_USP 0x4 +#define CXL_PORT_CONFIG_STATE_FABRIC_PORT 0x5 +#define CXL_PORT_CONFIG_STATE_INVALID_PORT_ID 0xF + +#define CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN 0x00 +#define CXL_PORT_CONNECTED_DEV_MODE_RCD 0x01 +#define CXL_PORT_CONNECTED_DEV_MODE_68B_VH 0x02 +#define CXL_PORT_CONNECTED_DEV_MODE_256B 0x03 +#define CXL_PORT_CONNECTED_DEV_MODE_LO_256B 0x04 +#define CXL_PORT_CONNECTED_DEV_MODE_PBR 0x05 + +#define CXL_PORT_CONNECTED_DEV_TYPE_NONE 0x00 +#define CXL_PORT_CONNECTED_DEV_TYPE_PCIE 0x01 +#define CXL_PORT_CONNECTED_DEV_TYPE_1 0x02 +#define CXL_PORT_CONNECTED_DEV_TYPE_2_OR_HBR_SWITCH 0x03 +#define CXL_PORT_CONNECTED_DEV_TYPE_3_SLD 0x04 +#define CXL_PORT_CONNECTED_DEV_TYPE_3_MLD 0x05 +#define CXL_PORT_CONNECTED_DEV_PBR_COMPONENT 0x06 + +#define CXL_PORT_SUPPORTS_RCD BIT(0) +#define CXL_PORT_SUPPORTS_68B_VH BIT(1) +#define CXL_PORT_SUPPORTS_256B BIT(2) +#define CXL_PORT_SUPPORTS_LO_256B BIT(3) +#define CXL_PORT_SUPPORTS_PBR BIT(4) + +#define CXL_PORT_LTSSM_DETECT 0x00 +#define CXL_PORT_LTSSM_POLLING 0x01 +#define CXL_PORT_LTSSM_CONFIGURATION 0x02 +#define CXL_PORT_LTSSM_RECOVERY 0x03 +#define CXL_PORT_LTSSM_L0 0x04 +#define CXL_PORT_LTSSM_L0S 0x05 +#define CXL_PORT_LTSSM_L1 0x06 +#define CXL_PORT_LTSSM_L2 0x07 +#define CXL_PORT_LTSSM_DISABLED 0x08 +#define CXL_PORT_LTSSM_LOOPBACK 0x09 +#define CXL_PORT_LTSSM_HOT_RESET 0x0A + +#define CXL_PORT_LINK_STATE_FLAG_LANE_REVERSED BIT(0) +#define CXL_PORT_LINK_STATE_FLAG_PERST_ASSERTED BIT(1) +#define CXL_PORT_LINK_STATE_FLAG_PRSNT BIT(2) +#define CXL_PORT_LINK_STATE_FLAG_POWER_OFF BIT(3) + +#endif /* CXL_PORT_H */ --=20 MST