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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Bernhard Beschow , =?utf-8?B?SGVydsOp?= Poussineau , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Aurelien Jarno Subject: [PULL v3 44/62] hw/isa/piix: Share PIIX3's base class with PIIX4 Message-ID: <7d6f26594bc1ea1f9e7d115051e63c3a71cf0b60.1697966402.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697966752914100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bernhard Beschow Having a common base class will allow for futher code sharing between PIIX3= and PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20231007123843.127151-24-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin --- hw/isa/piix.c | 85 ++++++++++++++++++--------------------------------- 1 file changed, 30 insertions(+), 55 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index bd66fb7475..8f7d6c56a8 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -38,10 +38,6 @@ #include "migration/vmstate.h" #include "hw/acpi/acpi_aml_interface.h" =20 -typedef struct PIIXState PIIX4State; - -DECLARE_INSTANCE_CHECKER(PIIX4State, PIIX4_PCI_DEVICE, TYPE_PIIX4_PCI_DEVI= CE) - static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) { qemu_set_irq(piix3->isa_irqs_in[pic_irq], @@ -88,7 +84,7 @@ static void piix3_set_irq(void *opaque, int pirq, int lev= el) static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; PCIBus *bus =3D pci_get_bus(&s->dev); =20 /* now we change the pic irq level according to the piix irq mappings = */ @@ -108,7 +104,7 @@ static void piix4_set_irq(void *opaque, int irq_num, in= t level) =20 static void piix_request_i8259_irq(void *opaque, int irq, int level) { - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; qemu_set_irq(s->cpu_intr, level); } =20 @@ -156,8 +152,9 @@ static void piix3_write_config(PCIDevice *dev, } } =20 -static void piix_reset(PIIXState *d) +static void piix_reset(DeviceState *dev) { + PIIXState *d =3D PIIX_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; =20 pci_conf[0x04] =3D 0x07; /* master, memory and I/O */ @@ -196,13 +193,6 @@ static void piix_reset(PIIXState *d) d->rcr =3D 0; } =20 -static void piix3_reset(DeviceState *dev) -{ - PIIXState *d =3D PIIX_PCI_DEVICE(dev); - - piix_reset(d); -} - static int piix3_post_load(void *opaque, int version_id) { PIIXState *piix3 =3D opaque; @@ -227,7 +217,7 @@ static int piix3_post_load(void *opaque, int version_id) =20 static int piix4_post_load(void *opaque, int version_id) { - PIIX4State *s =3D opaque; + PIIXState *s =3D opaque; =20 if (version_id =3D=3D 2) { s->rcr =3D 0; @@ -291,8 +281,8 @@ static const VMStateDescription vmstate_piix4 =3D { .minimum_version_id =3D 2, .post_load =3D piix4_post_load, .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX4State), - VMSTATE_UINT8_V(rcr, PIIX4State, 3), + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), VMSTATE_END_OF_LIST() } }; @@ -426,7 +416,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *= scope) qbus_build_aml(bus, scope); } =20 -static void pci_piix3_init(Object *obj) +static void pci_piix_init(Object *obj) { PIIXState *d =3D PIIX_PCI_DEVICE(obj); =20 @@ -434,7 +424,6 @@ static void pci_piix3_init(Object *obj) ISA_NUM_IRQS); =20 object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } =20 static Property pci_piix3_props[] =3D { @@ -447,27 +436,22 @@ static Property pci_piix3_props[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static void pci_piix3_class_init(ObjectClass *klass, void *data) +static void pci_piix_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc =3D ACPI_DEV_AML_IF_CLASS(klass); =20 - k->config_write =3D piix3_write_config; - dc->reset =3D piix3_reset; + dc->reset =3D piix_reset; dc->desc =3D "ISA bridge"; - dc->vmsd =3D &vmstate_piix3; dc->hotpluggable =3D false; k->vendor_id =3D PCI_VENDOR_ID_INTEL; - /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ - k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; k->class_id =3D PCI_CLASS_BRIDGE_ISA; /* - * Reason: part of PIIX3 southbridge, needs to be wired up by + * Reason: part of PIIX southbridge, needs to be wired up by e.g. * pc_piix.c's pc_init1() */ dc->user_creatable =3D false; - device_class_set_props(dc, pci_piix3_props); adevc->build_dev_aml =3D build_pci_isa_aml; } =20 @@ -475,9 +459,9 @@ static const TypeInfo piix_pci_type_info =3D { .name =3D TYPE_PIIX_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PIIXState), - .instance_init =3D pci_piix3_init, + .instance_init =3D pci_piix_init, .abstract =3D true, - .class_init =3D pci_piix3_class_init, + .class_init =3D pci_piix_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { TYPE_ACPI_DEV_AML_IF }, @@ -500,22 +484,36 @@ static void piix3_realize(PCIDevice *dev, Error **err= p) pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } =20 +static void piix3_init(Object *obj) +{ + PIIXState *d =3D PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); +} + static void piix3_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 + k->config_write =3D piix3_write_config; k->realize =3D piix3_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd =3D &vmstate_piix3; + device_class_set_props(dc, pci_piix3_props); } =20 static const TypeInfo piix3_info =3D { .name =3D TYPE_PIIX3_DEVICE, .parent =3D TYPE_PIIX_PCI_DEVICE, + .instance_init =3D piix3_init, .class_init =3D piix3_class_init, }; =20 static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *s =3D PIIX4_PCI_DEVICE(dev); + PIIXState *s =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; qemu_irq *i8259_out_irq; @@ -584,18 +582,10 @@ static void piix4_realize(PCIDevice *dev, Error **err= p) pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); } =20 -static void piix4_isa_reset(DeviceState *dev) -{ - PIIX4State *s =3D PIIX4_PCI_DEVICE(dev); - - piix_reset(s); -} - static void piix4_init(Object *obj) { - PIIX4State *s =3D PIIX4_PCI_DEVICE(obj); + PIIXState *s =3D PIIX_PCI_DEVICE(obj); =20 - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); =20 @@ -610,30 +600,15 @@ static void piix4_class_init(ObjectClass *klass, void= *data) PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->realize =3D piix4_realize; - k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id =3D PCI_CLASS_BRIDGE_ISA; - dc->reset =3D piix4_isa_reset; - dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable =3D false; - dc->hotpluggable =3D false; } =20 static const TypeInfo piix4_info =3D { .name =3D TYPE_PIIX4_PCI_DEVICE, - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIX4State), + .parent =3D TYPE_PIIX_PCI_DEVICE, .instance_init =3D piix4_init, .class_init =3D piix4_class_init, - .interfaces =3D (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, }; =20 static void piix3_register_types(void) --=20 MST