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x=1612055306; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qHmpHK7fMKpNGGhV9Hhlvy1FKVh4htbFkoX5Q5QqcLg=; b=MfztiVEChcG0LHHSyeCsGOwxMCYYL3tefaSLFhnbgndLJzD2utAyvZ4S jccsZhnIGPiSSVM1zmQOPYvDxa89la/esSC7ZRWlRc7v9saOCRl03yrss NdQ4TEGTQKk7hRYcA5ZoFYy2cWvckb8SUT/n2AAnVDstg3fL+4HCjepQG t6VnYBJb2x/QxzrbnXErsflRYhzcz7RJKRN+xdScUjQKJmiJRc1kbfIt6 O+dWCDFZk6IWGh2kY8zreieIYLKAq/LqpJ16iMbK1GKasG8zaSDgHU90E +rGPhtBX03zzhSggzCgpErjTMOAB6Y4SiZYAl2mhKxTbpbCUvRjeZ0s+3 w==; IronPort-SDR: grma4uEqsKthSrLxvnTt/141IKHrFi4/cpW3cSBUKwniBVb3LB3Ysl4gr1HBv/9wL9gSbybssh IduILATd3MfupYZxQh7dlXUaQxdx8P6AHqB2LvlosPk1RpLR5qxOyG8Nv20TAFsrkwoO3rK9Xs XL9qnQFytJydmuc+HcCMoMlQIorrGWso8bXPtmRR0VcMERVj73mceKguR+1oz96SSM47H67Bbf OLJAbUU3G4VsQ6zsDZFKQ5kGhYqTN8c/br/FUYPOXb6DdtnGBcbQyvPZ8VVftYzyBOIunrOvG1 72A= X-IronPort-AV: E=Sophos;i="5.70,388,1574092800"; d="scan'208";a="128872404" IronPort-SDR: ZEHBl/Bs84AP1MgveHDtj6+WxSltm5yofuGIp5cXTlTHyFNKhRzWtRR52DkeY5MdulIQKRtkjP LtoG2kNvSd+k4sRZPMINW7qDCPYkJuLafD4kBFXKms9YO2kUOj++gjA0GSJpRmfjDRrXatMX9z xfpQikTGb+Cm65scKSeAwDcG0+xnzu/6HUdbVay6KtvNWfEUCGr4pOFsjvio8XDr0I9bIpXJOo 6WSBrxxL1k32lcdrgeFwp+QAZZvjy1Dzh8yvCYzD9SNwa+HKibSgE1Wo4clED7g6Qul2mWRmvf d8WmPj4UENVWL5cOuE/0Lkr8 IronPort-SDR: aiuFksYtyuxjj1i78HV/cOnorUUGUOiNwS8f/1vXTppCkEUaII/CKgEL+SjtY8hNYA8jX18KhM mbhWTZRgG1q5XPziPunQZiVnbrFdlnGlvFvqiQHJpP2sZpM/8MeYDnDTNJjj093GFIDFXMKvcT z7GYo8KsvuGGQX9puOfuOBl5NL4U+54NGaSjrPm0RraoVDmwAhbOaiUX1U3KqRrslfa92Xo7Q1 CgRSnRvGNN0J8Z2HWuJA+j5e9lihIORi1sePBhGh0K06obDLnICvs5Sja/SXyrp0Q+Z/5sFqq/ EIY= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs Date: Fri, 31 Jan 2020 17:01:49 -0800 Message-Id: <7d2a69b0dab41c20e1e7aa186596040fb50423e5.1580518859.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 6 +++--- target/riscv/cpu_bits.h | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2f62f5ea19..f7a35c74c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -80,14 +80,14 @@ const char * const riscv_excp_names[] =3D { const char * const riscv_intr_names[] =3D { "u_software", "s_software", - "h_software", + "vs_software", "m_software", "u_timer", "s_timer", - "h_timer", + "vs_timer", "m_timer", "u_external", - "s_external", + "vs_external", "h_external", "m_external", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9ce73c36de..eeaa03c0f8 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -514,29 +514,29 @@ /* Interrupt causes */ #define IRQ_U_SOFT 0 #define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 /* reserved */ +#define IRQ_VS_SOFT 2 #define IRQ_M_SOFT 3 #define IRQ_U_TIMER 4 #define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 /* reserved */ +#define IRQ_VS_TIMER 6 #define IRQ_M_TIMER 7 #define IRQ_U_EXT 8 #define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 /* reserved */ +#define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 =20 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_VSSIP (1 << IRQ_VS_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) #define MIP_UTIP (1 << IRQ_U_TIMER) #define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_VSTIP (1 << IRQ_VS_TIMER) #define MIP_MTIP (1 << IRQ_M_TIMER) #define MIP_UEIP (1 << IRQ_U_EXT) #define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) =20 /* sip masks */ --=20 2.25.0