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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=66.111.4.29; envelope-from=alistair@alistair23.me; helo=out5-smtp.messagingengine.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 14:02:38 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis --- hw/riscv/opentitan.c | 19 +++++++++++++++++-- include/hw/riscv/opentitan.h | 3 +++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 1f9f4a8dd0..3a845fbb7b 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -25,6 +25,7 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "exec/address-spaces.h" +#include "sysemu/sysemu.h" =20 static const struct MemmapEntry { hwaddr base; @@ -92,6 +93,9 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); + + sysbus_init_child_obj(obj, "plic", &s->plic, + sizeof(s->plic), TYPE_IBEX_PLIC); } =20 static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **e= rrp) @@ -100,6 +104,9 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState = *dev_soc, Error **errp) MachineState *ms =3D MACHINE(qdev_get_machine()); LowRISCIbexSoCState *s =3D RISCV_IBEX_SOC(dev_soc); MemoryRegion *sys_mem =3D get_system_memory(); + DeviceState *dev; + SysBusDevice *busdev; + Error *err =3D NULL; =20 object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", &error_abort); @@ -120,6 +127,16 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState= *dev_soc, Error **errp) memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base, &s->flash_mem); =20 + /* PLIC */ + dev =3D DEVICE(&s->plic); + object_property_set_bool(OBJECT(&s->plic), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, memmap[IBEX_PLIC].base); + create_unimplemented_device("riscv.lowrisc.ibex.uart", memmap[IBEX_UART].base, memmap[IBEX_UART].size); create_unimplemented_device("riscv.lowrisc.ibex.gpio", @@ -134,8 +151,6 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState = *dev_soc, Error **errp) memmap[IBEX_AES].base, memmap[IBEX_AES].size); create_unimplemented_device("riscv.lowrisc.ibex.hmac", memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size); - create_unimplemented_device("riscv.lowrisc.ibex.plic", - memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size); create_unimplemented_device("riscv.lowrisc.ibex.pinmux", memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size); create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 15a3d87ed0..8d6a09b696 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -20,6 +20,7 @@ #define HW_OPENTITAN_H =20 #include "hw/riscv/riscv_hart.h" +#include "hw/intc/ibex_plic.h" =20 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" #define RISCV_IBEX_SOC(obj) \ @@ -31,6 +32,8 @@ typedef struct LowRISCIbexSoCState { =20 /*< public >*/ RISCVHartArrayState cpus; + IbexPlicState plic; + MemoryRegion flash_mem; MemoryRegion rom; } LowRISCIbexSoCState; --=20 2.26.2