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X-Received-From: 68.232.143.124 Subject: [Qemu-devel] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=3D0) register. Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 1e7e4c8d51..25da29fa3d 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -147,7 +147,17 @@ static void sifive_plic_update(SiFivePLICState *plic) riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(le= vel)); break; case PLICMode_S: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(le= vel)); + if (riscv_cpu_virt_enabled(env)) { + if (level) { + atomic_or(&env->bsip, MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } else { + atomic_and(&env->bsip, ~MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } + } else { + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MAS= K(level)); + } break; default: break; --=20 2.21.0