From nobody Mon Feb 9 20:12:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15289364571691022.6509474252138; Wed, 13 Jun 2018 17:34:17 -0700 (PDT) Received: from localhost ([::1]:37446 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTGDH-0007d0-96 for importer@patchew.org; Wed, 13 Jun 2018 20:34:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fTGBF-0006O3-HY for qemu-devel@nongnu.org; Wed, 13 Jun 2018 20:32:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fTGBC-00037S-BX for qemu-devel@nongnu.org; Wed, 13 Jun 2018 20:32:01 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:32734) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fTGBC-000370-4H; Wed, 13 Jun 2018 20:31:58 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 53E8F7456B3; Thu, 14 Jun 2018 02:31:56 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 767937456B4; Thu, 14 Jun 2018 02:31:55 +0200 (CEST) Message-Id: <7a407b15b683417745e71a95452d5094e6e9fe94.1528935420.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Thu, 14 Jun 2018 02:17:00 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH v3 6/9] sm501: Do not clear read only bits when writing registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When writing registers that have read only bits we have to avoid changing these bits as they may have non zero values. Make sure we use the correct masks to mask out read only and reserved bits when changing registers. Also remove extra spaces from dram_control and arbitration_control assignments. Signed-off-by: BALATON Zoltan --- v3: Not only preserve read only bits but also allow clearing r/w bits hw/display/sm501.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index e47be99..ca0840f 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -836,27 +836,30 @@ static void sm501_system_config_write(void *opaque, h= waddr addr, =20 switch (addr) { case SM501_SYSTEM_CONTROL: - s->system_control =3D value & 0xE300B8F7; + s->system_control &=3D 0x10DB0000; + s->system_control |=3D value & 0xEF00B8F7; break; case SM501_MISC_CONTROL: - s->misc_control =3D value & 0xFF7FFF20; + s->misc_control &=3D 0xEF; + s->misc_control |=3D value & 0xFF7FFF10; break; case SM501_GPIO31_0_CONTROL: s->gpio_31_0_control =3D value; break; case SM501_GPIO63_32_CONTROL: - s->gpio_63_32_control =3D value; + s->gpio_63_32_control =3D value & 0xFF80FFFF; break; case SM501_DRAM_CONTROL: s->local_mem_size_index =3D (value >> 13) & 0x7; /* TODO : check validity of size change */ - s->dram_control |=3D value & 0x7FFFFFC3; + s->dram_control &=3D 0x80000000; + s->dram_control |=3D value & 0x7FFFFFC3; break; case SM501_ARBTRTN_CONTROL: - s->arbitration_control =3D value & 0x37777777; + s->arbitration_control =3D value & 0x37777777; break; case SM501_IRQ_MASK: - s->irq_mask =3D value; + s->irq_mask =3D value & 0xFFDF3F5F; break; case SM501_MISC_TIMING: s->misc_timing =3D value & 0xF31F1FFF; --=20 2.7.6