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Date: Wed, 15 Jan 2025 13:08:50 -0500
From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Zhenzhong Duan <zhenzhong.duan@intel.com>,
Yi Liu <yi.l.liu@intel.com>, Jason Wang <jasowang@redhat.com>,
=?utf-8?Q?Cl=C3=A9ment?= Mathieu--Drif <clement.mathieu--drif@eviden.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: [PULL 08/48] intel_iommu: Add a placeholder variable for scalable
mode stage-1 translation
Message-ID:
<791346f93d2aa3b7eaebf4a12f4b7c558e94ff6b.1736964488.git.mst@redhat.com>
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From: Zhenzhong Duan <zhenzhong.duan@intel.com>
Add an new element flts in IntelIOMMUState to mark stage-1 translation supp=
ort
in scalable mode, this element will be exposed as an intel_iommu property
x-flts finally.
For now, it's only a placehholder and used for address width compatibility
check and block host device passthrough until nesting is supported.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Cl=C3=A9ment Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-4-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 23 ++++++++++++++++++-----
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index d372cd396b..b19f3004f0 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -262,6 +262,7 @@ struct IntelIOMMUState {
=20
bool caching_mode; /* RO - is cap CM enabled? */
bool scalable_mode; /* RO - is Scalable Mode supported? */
+ bool flts; /* RO - is stage-1 translation support=
ed? */
bool snoop_control; /* RO - is SNP filed supported? */
=20
dma_addr_t root; /* Current root table pointer */
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index bd639b7ff7..d0c1d73974 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3917,7 +3917,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI=
OMMUDevice *hiod,
return false;
}
=20
- return true;
+ if (!s->flts) {
+ /* All checks requested by VTD stage-2 translation pass */
+ return true;
+ }
+
+ error_setg(errp, "host device is uncompatible with stage-1 translation=
");
+ return false;
}
=20
static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,
@@ -4307,14 +4313,21 @@ static bool vtd_decide_config(IntelIOMMUState *s, E=
rror **errp)
}
}
=20
- /* Currently only address widths supported are 39 and 48 bits */
- if ((s->aw_bits !=3D VTD_HOST_AW_39BIT) &&
- (s->aw_bits !=3D VTD_HOST_AW_48BIT)) {
- error_setg(errp, "Supported values for aw-bits are: %d, %d",
+ if (!s->flts && s->aw_bits !=3D VTD_HOST_AW_39BIT &&
+ s->aw_bits !=3D VTD_HOST_AW_48BIT) {
+ error_setg(errp, "%s: supported values for aw-bits are: %d, %d",
+ s->scalable_mode ? "Scalable mode(flts=3Doff)" : "Legac=
y mode",
VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT);
return false;
}
=20
+ if (s->flts && s->aw_bits !=3D VTD_HOST_AW_48BIT) {
+ error_setg(errp,
+ "Scalable mode(flts=3Don): supported value for aw-bits =
is: %d",
+ VTD_HOST_AW_48BIT);
+ return false;
+ }
+
if (s->scalable_mode && !s->dma_drain) {
error_setg(errp, "Need to set dma_drain for scalable mode");
return false;
--=20
MST