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Fri, 16 Jan 2026 20:27:40 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 1/8] riscv: split sdext and sdtrig config bits Date: Sat, 17 Jan 2026 12:27:22 +0800 Message-ID: <78122e119ee8c961716e2bec72c9895148b04ef9.1768622882.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pg1-x542.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624577171158500 Content-Type: text/plain; charset="utf-8" Add cfg.ext_sdext and cfg.ext_sdtrig and expose them as ISA extensions. Keep the legacy 'debug' CPU property as a global kill switch and force-disable both when it is off. Trigger CSRs (tselect/tdata*/tinfo/mcontext) and trigger setup now depend on ext_sdtrig instead of cfg.debug. Signed-off-by: Chao Liu --- target/riscv/cpu.c | 18 +++++++++++++++--- target/riscv/cpu_cfg_fields.h.inc | 2 ++ target/riscv/csr.c | 16 ++++++++-------- target/riscv/machine.c | 4 ++-- target/riscv/tcg/tcg-cpu.c | 11 +---------- 5 files changed, 28 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73d4280d7c..bc0b385cc1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -189,7 +189,8 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), - ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug), + ISA_EXT_DATA_ENTRY(sdext, PRIV_VERSION_1_12_0, ext_sdext), + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha), ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -783,7 +784,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType= type) env->vill =3D true; =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } =20 @@ -922,6 +923,15 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error = **errp) return; } } + + /* + * Keep the legacy 'debug' CPU property as a global kill switch. + * If it is off, force-disable Sdext/Sdtrig regardless of ISA strings. + */ + if (!cpu->cfg.debug) { + cpu->cfg.ext_sdext =3D false; + cpu->cfg.ext_sdtrig =3D false; + } } =20 static void riscv_cpu_realize(DeviceState *dev, Error **errp) @@ -946,7 +956,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) riscv_cpu_register_gdb_regs_for_features(cs); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_realize(&cpu->env); } #endif @@ -1112,6 +1122,8 @@ static void riscv_cpu_init(Object *obj) */ RISCV_CPU(obj)->cfg.ext_zicntr =3D !mcc->def->bare; RISCV_CPU(obj)->cfg.ext_zihpm =3D !mcc->def->bare; + RISCV_CPU(obj)->cfg.ext_sdext =3D true; + RISCV_CPU(obj)->cfg.ext_sdtrig =3D true; =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index a154ecdc79..9701319195 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -44,6 +44,8 @@ BOOL_FIELD(ext_zihpm) BOOL_FIELD(ext_zimop) BOOL_FIELD(ext_zcmop) BOOL_FIELD(ext_ztso) +BOOL_FIELD(ext_sdext) +BOOL_FIELD(ext_sdtrig) BOOL_FIELD(ext_smstateen) BOOL_FIELD(ext_sstc) BOOL_FIELD(ext_smcdeleg) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c91658c3d..4f071b1db2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -775,9 +775,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 -static RISCVException debug(CPURISCVState *env, int csrno) +static RISCVException sdtrig(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->debug) { + if (riscv_cpu_cfg(env)->ext_sdtrig) { return RISCV_EXCP_NONE; } =20 @@ -6308,12 +6308,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 /* Debug CSRs */ - [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect= }, - [CSR_TDATA1] =3D { "tdata1", debug, read_tdata, write_tdata = }, - [CSR_TDATA2] =3D { "tdata2", debug, read_tdata, write_tdata = }, - [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata = }, - [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore = }, - [CSR_MCONTEXT] =3D { "mcontext", debug, read_mcontext, write_mcontex= t }, + [CSR_TSELECT] =3D { "tselect", sdtrig, read_tselect, write_tselec= t }, + [CSR_TDATA1] =3D { "tdata1", sdtrig, read_tdata, write_tdata = }, + [CSR_TDATA2] =3D { "tdata2", sdtrig, read_tdata, write_tdata = }, + [CSR_TDATA3] =3D { "tdata3", sdtrig, read_tdata, write_tdata = }, + [CSR_TINFO] =3D { "tinfo", sdtrig, read_tinfo, write_ignore= }, + [CSR_MCONTEXT] =3D { "mcontext", sdtrig, read_mcontext, write_mconte= xt }, =20 [CSR_MCTRCTL] =3D { "mctrctl", ctr_mmode, NULL, NULL, rmw_xctrc= tl }, [CSR_SCTRCTL] =3D { "sctrctl", ctr_smode, NULL, NULL, rmw_xctrc= tl }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 18d790af0d..d6a0b8e357 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -222,7 +222,7 @@ static bool debug_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.debug; + return cpu->cfg.ext_sdext || cpu->cfg.ext_sdtrig; } =20 static int debug_post_load(void *opaque, int version_id) @@ -230,7 +230,7 @@ static int debug_post_load(void *opaque, int version_id) RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; =20 - if (icount_enabled()) { + if (cpu->cfg.ext_sdtrig && icount_enabled()) { env->itrigger_enabled =3D riscv_itrigger_enabled(env); } =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index d3968251fa..b5a26cf662 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -177,7 +177,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; } =20 - if (cpu->cfg.debug && !icount_enabled()) { + if (cpu->cfg.ext_sdtrig && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } #endif @@ -469,15 +469,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) continue; } =20 - /* - * cpu.debug =3D true is marked as 'sdtrig', priv spec 1.12. - * Skip this warning since existing CPUs with older priv - * spec and debug =3D true will be impacted. - */ - if (!strcmp(edata->name, "sdtrig")) { - continue; - } - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); =20 /* --=20 2.52.0