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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id e65-20020a0dc244000000b0056cffe97a11sm604604ywd.13.2023.06.20.10.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:26:15 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8f95edf0-0f8f-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281975; x=1689873975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5oficzjs5xcBYSHcpYrMTcfh+AwyMWQx/k5j2kJ4DGo=; b=O2gmxwgPbbW0ycNLE6VtVZ2j4XzYDPo99Wh8EBMogWPXV+Kpoo9l2hXiGgJTL+3UWy AV3HvB2nSQNIdHMZ3w/fcuOS3koy85JWsyMEA7Yff+X+tkkHnwQAUrI+P7vHfcJew7Ug Xm/I3seDw2cBPzJ85DqXi1QSKXudjAHLntTZvTgkwyQs8QodwBBGFOhFsBa9wdc+0HRV HC+t05bwvGK34OqN7tNbN9nZ4fHb12xARVgPdXFx+ua4ql/xGu5zg7kk2qyn2rHk3n0l 9IaX5IlOAWeqfzqzljQHBqfCYEO5CzgHpqTA/ZiuAQed4J4/mx+PjRPgfZHTOe0RL5mE DujQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281975; x=1689873975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5oficzjs5xcBYSHcpYrMTcfh+AwyMWQx/k5j2kJ4DGo=; b=EJVJY8eWd9JJWyqHFcMDyvdMQ27K5DuILLi9pNmXp6Nv/Xk+tZ3sHOm1YX+vxI1sBD MjlFGRvSlGKepiySkziYNPPNtzJa6C9b/Cb/G9fWvXFGYmj6M9ayiVd+Nz3e/+tVq9Vd 8xX24D1ZzEIH5Ev5hWMKZdzloEPmxJxlCK9U7p/0jc1nGAE/KVNqCEuXZy64L178NV2U mrG2g4hPE9xQP9SE1hMZmmAVnP0P1vlC87yyZk6ZAECGlhkL5bFIPfXyeqFB1zN/ajVJ OGz4S4kcQJj+T1a5JgrFeTkqJzcJMtNUX43wq7ql2OpFiiED3WhkqWKldTm29KuLRZOw vzEw== X-Gm-Message-State: AC+VfDzT0r3S5e5xRfrKBF/niXqsb0F0BexwlCVmXzEEfirU5SJejhxx 1xjCk6e4QbOpVJrSJHBFhMA= X-Google-Smtp-Source: ACHHUZ6XnSFKFEmZ4JRuuQ8RG5O/zfoeupAWUrMFLcGCPcnHuHkd+hGqCOhfxRag80J/Ukwvt5V6wQ== X-Received: by 2002:a81:6ac6:0:b0:56d:ccf:19a9 with SMTP id f189-20020a816ac6000000b0056d0ccf19a9mr16316679ywc.34.1687281975343; Tue, 20 Jun 2023 10:26:15 -0700 (PDT) From: Joel Upham To: qemu-devel@nongnu.org Cc: Joel Upham , Stefano Stabellini , Anthony Perard , Paul Durrant , xen-devel@lists.xenproject.org (open list:X86 Xen CPUs) Subject: [PATCH v1 10/23] xen/pt: add support for PCIe Extended Capabilities and larger config space Date: Tue, 20 Jun 2023 13:24:44 -0400 Message-Id: <775c2acb6ac819990e28d881167fcdfcd58b9886.1687278381.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1687282004444100003 Content-Type: text/plain; charset="utf-8" This patch provides basic facilities for PCIe Extended Capabilities and support for controlled (via s->pcie_enabled_dev flag) access to PCIe config space (>256). PCIe Extended Capabilities make use of 16-bit capability ID. Also, a capability size might exceed 8-bit width. So as the very first step we need to increase type size for grp_id, grp_size, etc -- they were limited to 8-bit. The only troublesome issue with PCIe Extended Capability IDs is that their value range is actually same as for basic PCI capabilities. Eg. capability ID 3 means VPD Capability for PCI and at the same time Device Serial Number Capability for PCIe Extended caps. This adds a bit of inconvenience. In order to distinguish between two sets of same capability IDs, the patch introduces a set of macros to mark a capability ID as PCIe Extended one (or check if it is basic/extended + get a raw ID value): - PCIE_EXT_CAP_ID(cap_id) - IS_PCIE_EXT_CAP_ID(grp_id) - GET_PCIE_EXT_CAP_ID(grp_id) Here is how it's used: /* Intel IGD Opregion group */ { .grp_id =3D XEN_PCI_INTEL_OPREGION, /* no change */ .grp_type =3D XEN_PT_GRP_TYPE_EMU, .grp_size =3D 0x4, .size_init =3D xen_pt_reg_grp_size_init, .emu_regs =3D xen_pt_emu_reg_igd_opregion, }, /* Vendor-specific Extended Capability reg group */ { .grp_id =3D PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_VNDR), .grp_type =3D XEN_PT_GRP_TYPE_EMU, .grp_size =3D 0xFF, .size_init =3D xen_pt_ext_cap_vendor_size_init, .emu_regs =3D xen_pt_ext_cap_emu_reg_vendor, }, By using the PCIE_EXT_CAP_ID() macro it is possible to reuse existing header files with already defined PCIe Extended Capability ID values. find_cap_offset() receive capabily ID and checks if it's an Extended one by using IS_PCIE_EXT_CAP_ID(cap) macro, passing the real capabiliy ID value to either xen_host_pci_find_next_ext_cap or xen_host_pci_find_next_cap. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- hw/xen/xen_pt.c | 10 ++++- hw/xen/xen_pt.h | 13 ++++-- hw/xen/xen_pt_config_init.c | 90 ++++++++++++++++++++++++++----------- 3 files changed, 83 insertions(+), 30 deletions(-) diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index 65c5516ef4..f757978800 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -96,8 +96,16 @@ void xen_pt_log(const PCIDevice *d, const char *f, ...) =20 static int xen_pt_pci_config_access_check(PCIDevice *d, uint32_t addr, int= len) { + XenPCIPassthroughState *s =3D XEN_PT_DEVICE(d); /* check offset range */ - if (addr > 0xFF) { + if (s->pcie_enabled_dev) { + if (addr >=3D PCIE_CONFIG_SPACE_SIZE) { + XEN_PT_ERR(d, "Failed to access register with offset " + "exceeding 0xFFF. (addr: 0x%02x, len: %d)\n", + addr, len); + return -1; + } + } else if (addr >=3D PCI_CONFIG_SPACE_SIZE) { XEN_PT_ERR(d, "Failed to access register with offset exceeding 0xF= F. " "(addr: 0x%02x, len: %d)\n", addr, len); return -1; diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h index 1c9cd6b615..eb062be3f4 100644 --- a/hw/xen/xen_pt.h +++ b/hw/xen/xen_pt.h @@ -33,6 +33,11 @@ void xen_pt_log(const PCIDevice *d, const char *f, ...) = G_GNUC_PRINTF(2, 3); /* Helper */ #define XEN_PFN(x) ((x) >> XC_PAGE_SHIFT) =20 +/* Macro's for PCIe Extended Capabilities */ +#define PCIE_EXT_CAP_ID(cap_id) ((cap_id) | (1U << 16)) +#define IS_PCIE_EXT_CAP_ID(grp_id) ((grp_id) & (1U << 16)) +#define GET_PCIE_EXT_CAP_ID(grp_id) ((grp_id) & 0xFFFF) + typedef const struct XenPTRegInfo XenPTRegInfo; typedef struct XenPTReg XenPTReg; =20 @@ -174,13 +179,13 @@ typedef const struct XenPTRegGroupInfo XenPTRegGroupI= nfo; /* emul reg group size initialize method */ typedef int (*xen_pt_reg_size_init_fn) (XenPCIPassthroughState *, XenPTRegGroupInfo *, - uint32_t base_offset, uint8_t *size); + uint32_t base_offset, uint32_t *size); =20 /* emulated register group information */ struct XenPTRegGroupInfo { - uint8_t grp_id; + uint32_t grp_id; XenPTRegisterGroupType grp_type; - uint8_t grp_size; + uint32_t grp_size; xen_pt_reg_size_init_fn size_init; XenPTRegInfo *emu_regs; }; @@ -190,7 +195,7 @@ typedef struct XenPTRegGroup { QLIST_ENTRY(XenPTRegGroup) entries; XenPTRegGroupInfo *reg_grp; uint32_t base_offset; - uint8_t size; + uint32_t size; QLIST_HEAD(, XenPTReg) reg_tbl_list; } XenPTRegGroup; =20 diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index 757a035aad..34ed9c25c5 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -32,28 +32,40 @@ static int xen_pt_ptr_reg_init(XenPCIPassthroughState *= s, XenPTRegInfo *reg, /* helper */ =20 /* A return value of 1 means the capability should NOT be exposed to guest= . */ -static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id) +static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint32_t grp_id) { - switch (grp_id) { - case PCI_CAP_ID_EXP: - /* The PCI Express Capability Structure of the VF of Intel 82599 1= 0GbE - * Controller looks trivial, e.g., the PCI Express Capabilities - * Register is 0. We should not try to expose it to guest. - * - * The datasheet is available at - * http://download.intel.com/design/network/datashts/82599_datashe= et.pdf - * - * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, = the - * PCI Express Capability Structure of the VF of Intel 82599 10GbE - * Controller looks trivial, e.g., the PCI Express Capabilities - * Register is 0, so the Capability Version is 0 and - * xen_pt_pcie_size_init() would fail. - */ - if (d->vendor_id =3D=3D PCI_VENDOR_ID_INTEL && - d->device_id =3D=3D PCI_DEVICE_ID_INTEL_82599_SFP_VF) { - return 1; + if (IS_PCIE_EXT_CAP_ID(grp_id)) { + switch (GET_PCIE_EXT_CAP_ID(grp_id)) { + /* Here can be added device-specific filtering + * for PCIe Extended capabilities (those with offset >=3D 0x10= 0). + * This is simply a placeholder as no filtering needed for now. + */ + default: + break; + } + } else { + /* basic PCI capability */ + switch (grp_id) { + case PCI_CAP_ID_EXP: + /* The PCI Express Capability Structure of the VF of Intel 825= 99 10GbE + * Controller looks trivial, e.g., the PCI Express Capabilities + * Register is 0. We should not try to expose it to guest. + * + * The datasheet is available at + * http://download.intel.com/design/network/datashts/82599_dat= asheet.pdf + * + * See 'Table 9.7. VF PCIe Configuration Space' of the datashe= et, the + * PCI Express Capability Structure of the VF of Intel 82599 1= 0GbE + * Controller looks trivial, e.g., the PCI Express Capabilities + * Register is 0, so the Capability Version is 0 and + * xen_pt_pcie_size_init() would fail. + */ + if (d->vendor_id =3D=3D PCI_VENDOR_ID_INTEL && + d->device_id =3D=3D PCI_DEVICE_ID_INTEL_82599_SFP_VF) { + return 1; + } + break; } - break; } return 0; } @@ -1615,7 +1627,7 @@ static XenPTRegInfo xen_pt_emu_reg_igd_opregion[] =3D= { =20 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s, const XenPTRegGroupInfo *grp_reg, - uint32_t base_offset, uint8_t *size) + uint32_t base_offset, uint32_t *size) { *size =3D grp_reg->grp_size; return 0; @@ -1623,14 +1635,22 @@ static int xen_pt_reg_grp_size_init(XenPCIPassthrou= ghState *s, /* get Vendor Specific Capability Structure register group size */ static int xen_pt_vendor_size_init(XenPCIPassthroughState *s, const XenPTRegGroupInfo *grp_reg, - uint32_t base_offset, uint8_t *size) + uint32_t base_offset, uint32_t *size) +{ + uint8_t sz =3D 0; + int ret =3D xen_host_pci_get_byte(&s->real_device, base_offset + 0x02,= &sz); + + *size =3D sz; + return ret; +} + { return xen_host_pci_get_byte(&s->real_device, base_offset + 0x02, size= ); } /* get PCI Express Capability Structure register group size */ static int xen_pt_pcie_size_init(XenPCIPassthroughState *s, const XenPTRegGroupInfo *grp_reg, - uint32_t base_offset, uint8_t *size) + uint32_t base_offset, uint32_t *size) { PCIDevice *d =3D PCI_DEVICE(s); uint8_t version =3D get_pcie_capability_version(s); @@ -1702,7 +1722,7 @@ static int xen_pt_pcie_size_init(XenPCIPassthroughSta= te *s, /* get MSI Capability Structure register group size */ static int xen_pt_msi_size_init(XenPCIPassthroughState *s, const XenPTRegGroupInfo *grp_reg, - uint32_t base_offset, uint8_t *size) + uint32_t base_offset, uint32_t *size) { uint16_t msg_ctrl =3D 0; uint8_t msi_size =3D 0xa; @@ -1730,7 +1750,7 @@ static int xen_pt_msi_size_init(XenPCIPassthroughStat= e *s, /* get MSI-X Capability Structure register group size */ static int xen_pt_msix_size_init(XenPCIPassthroughState *s, const XenPTRegGroupInfo *grp_reg, - uint32_t base_offset, uint8_t *size) + uint32_t base_offset, uint32_t *size) { int rc =3D 0; =20 @@ -1953,6 +1973,26 @@ static uint8_t find_cap_offset(XenPCIPassthroughStat= e *s, uint8_t cap) return 0; } =20 +/************* + * Main + */ + +static uint32_t find_cap_offset(XenPCIPassthroughState *s, uint32_t cap) +{ + uint32_t retval =3D 0; + + if (IS_PCIE_EXT_CAP_ID(cap)) { + if (s->pcie_enabled_dev) { + retval =3D xen_host_pci_find_next_ext_cap(&s->real_device, 0, + GET_PCIE_EXT_CAP_ID(ca= p)); + } + + } else { + retval =3D xen_host_pci_find_next_cap(&s->real_device, 0, cap); + } + return retval; +} + static void xen_pt_config_reg_init(XenPCIPassthroughState *s, XenPTRegGroup *reg_grp, XenPTRegInfo *r= eg, Error **errp) --=20 2.34.1