From nobody Tue Feb 10 11:15:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162570677453085.1069672665385; Wed, 7 Jul 2021 18:12:54 -0700 (PDT) Received: from localhost ([::1]:60256 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1Iay-00036v-9Q for importer@patchew.org; Wed, 07 Jul 2021 21:12:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKs-0002Aw-08 for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:17 -0400 Received: from mga12.intel.com ([192.55.52.136]:57610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1IKp-0007LH-Iy for qemu-devel@nongnu.org; Wed, 07 Jul 2021 20:56:13 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:59 -0700 Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2021 17:55:58 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="189101734" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="189101734" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="423770111" From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, pbonzini@redhat.com, alistair@alistair23.me, ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, cohuck@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com, seanjc@google.com, erdemaktas@google.com Subject: [RFC PATCH v2 37/44] hw/i386: add option to forcibly report edge trigger in acpi tables Date: Wed, 7 Jul 2021 17:55:07 -0700 Message-Id: <7348b3dd8450923bba9b52e6705bdce477197bef.1625704981.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.136; envelope-from=isaku.yamahata@intel.com; helo=mga12.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1625706774880100001 Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata When level trigger isn't supported on x86 platform, forcibly report edge trigger in acpi tables. Signed-off-by: Isaku Yamahata --- hw/i386/acpi-build.c | 103 ++++++++++++++++++++++++++++-------------- hw/i386/acpi-common.c | 74 ++++++++++++++++++++++-------- 2 files changed, 124 insertions(+), 53 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 796ffc6f5c..d0d52258b9 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -866,7 +866,8 @@ static void build_dbg_aml(Aml *table) aml_append(table, scope); } =20 -static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) +static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg, + bool level_trigger_unsupported) { Aml *dev; Aml *crs; @@ -878,7 +879,10 @@ static Aml *build_link_dev(const char *name, uint8_t u= id, Aml *reg) aml_append(dev, aml_name_decl("_UID", aml_int(uid))); =20 crs =3D aml_resource_template(); - aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + aml_append(crs, aml_interrupt(AML_CONSUMER, + level_trigger_unsupported ? + AML_EDGE : AML_LEVEL, + AML_ACTIVE_HIGH, AML_SHARED, irqs, ARRAY_SIZE(irqs))); aml_append(dev, aml_name_decl("_PRS", crs)); =20 @@ -902,7 +906,8 @@ static Aml *build_link_dev(const char *name, uint8_t ui= d, Aml *reg) return dev; } =20 -static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) +static Aml *build_gsi_link_dev(const char *name, uint8_t uid, + uint8_t gsi, bool level_trigger_unsupported) { Aml *dev; Aml *crs; @@ -915,7 +920,10 @@ static Aml *build_gsi_link_dev(const char *name, uint8= _t uid, uint8_t gsi) =20 crs =3D aml_resource_template(); irqs =3D gsi; - aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + aml_append(crs, aml_interrupt(AML_CONSUMER, + level_trigger_unsupported ? + AML_EDGE : AML_LEVEL, + AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); aml_append(dev, aml_name_decl("_PRS", crs)); =20 @@ -934,7 +942,7 @@ static Aml *build_gsi_link_dev(const char *name, uint8_= t uid, uint8_t gsi) } =20 /* _CRS method - get current settings */ -static Aml *build_iqcr_method(bool is_piix4) +static Aml *build_iqcr_method(bool is_piix4, bool level_trigger_unsupporte= d) { Aml *if_ctx; uint32_t irqs; @@ -942,7 +950,9 @@ static Aml *build_iqcr_method(bool is_piix4) Aml *crs =3D aml_resource_template(); =20 irqs =3D 0; - aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, + aml_append(crs, aml_interrupt(AML_CONSUMER, + level_trigger_unsupported ? + AML_EDGE : AML_LEVEL, AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); aml_append(method, aml_name_decl("PRR0", crs)); =20 @@ -976,7 +986,7 @@ static Aml *build_irq_status_method(void) return method; } =20 -static void build_piix4_pci0_int(Aml *table) +static void build_piix4_pci0_int(Aml *table, bool level_trigger_unsupporte= d) { Aml *dev; Aml *crs; @@ -997,12 +1007,16 @@ static void build_piix4_pci0_int(Aml *table) aml_append(sb_scope, field); =20 aml_append(sb_scope, build_irq_status_method()); - aml_append(sb_scope, build_iqcr_method(true)); + aml_append(sb_scope, build_iqcr_method(true, level_trigger_unsupported= )); =20 - aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); - aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); - aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); - aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); + aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"), + level_trigger_unsupported)); =20 dev =3D aml_device("LNKS"); { @@ -1011,7 +1025,9 @@ static void build_piix4_pci0_int(Aml *table) =20 crs =3D aml_resource_template(); irqs =3D 9; - aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, + aml_append(crs, aml_interrupt(AML_CONSUMER, + level_trigger_unsupported ? + AML_EDGE : AML_LEVEL, AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); aml_append(dev, aml_name_decl("_PRS", crs)); @@ -1097,7 +1113,7 @@ static Aml *build_q35_routing_table(const char *str) return pkg; } =20 -static void build_q35_pci0_int(Aml *table) +static void build_q35_pci0_int(Aml *table, bool level_trigger_unsupported) { Aml *field; Aml *method; @@ -1149,25 +1165,41 @@ static void build_q35_pci0_int(Aml *table) aml_append(sb_scope, field); =20 aml_append(sb_scope, build_irq_status_method()); - aml_append(sb_scope, build_iqcr_method(false)); - - aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); - aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); - aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); - aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); - aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); - aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); - aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); - aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); - - aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); - aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); - aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); - aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); - aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); - aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); - aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); - aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); + aml_append(sb_scope, build_iqcr_method(false, level_trigger_unsupporte= d)); + + aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"), + level_trigger_unsupported)); + aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"), + level_trigger_unsupported)); + + aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16, + level_trigger_unsupported)); + aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17, + level_trigger_unsupported)); =20 aml_append(table, sb_scope); } @@ -1370,6 +1402,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms =3D PC_MACHINE(machine); PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(machine); X86MachineState *x86ms =3D X86_MACHINE(machine); + bool level_trigger_unsupported =3D x86ms->eoi_intercept_unsupported; AcpiMcfgInfo mcfg; bool mcfg_valid =3D !!acpi_get_mcfg(&mcfg); uint32_t nr_mem =3D machine->ram_slots; @@ -1404,7 +1437,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, if (pm->pcihp_bridge_en || pm->pcihp_root_en) { build_piix4_pci_hotplug(dsdt); } - build_piix4_pci0_int(dsdt); + build_piix4_pci0_int(dsdt, level_trigger_unsupported); } else { sb_scope =3D aml_scope("_SB"); dev =3D aml_device("PCI0"); @@ -1450,7 +1483,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } build_q35_isa_bridge(dsdt); build_isa_devices_aml(dsdt); - build_q35_pci0_int(dsdt); + build_q35_pci0_int(dsdt, level_trigger_unsupported); if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); } diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c index 1f5947fcf9..90cb05a46d 100644 --- a/hw/i386/acpi-common.c +++ b/hw/i386/acpi-common.c @@ -80,6 +80,7 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *link= er, int madt_start =3D table_data->len; AcpiDeviceIfClass *adevc =3D ACPI_DEVICE_IF_GET_CLASS(adev); bool x2apic_mode =3D false; + bool level_trigger_unsupported =3D x86ms->eoi_intercept_unsupported; =20 AcpiMultipleApicTable *madt; AcpiMadtIoApic *io_apic; @@ -114,26 +115,63 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *= linker, io_apic2->interrupt =3D cpu_to_le32(IO_APIC_SECONDARY_IRQBASE); } =20 - if (x86ms->apic_xrupt_override) { - intsrcovr =3D acpi_data_push(table_data, sizeof *intsrcovr); - intsrcovr->type =3D ACPI_APIC_XRUPT_OVERRIDE; - intsrcovr->length =3D sizeof(*intsrcovr); - intsrcovr->source =3D 0; - intsrcovr->gsi =3D cpu_to_le32(2); - intsrcovr->flags =3D cpu_to_le16(0); /* conforms to bus specifica= tions */ - } + if (level_trigger_unsupported) { + /* Force edge trigger */ + if (x86ms->apic_xrupt_override) { + intsrcovr =3D acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type =3D ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length =3D sizeof(*intsrcovr); + intsrcovr->source =3D 0; + intsrcovr->gsi =3D cpu_to_le32(2); + /* active high, edge triggered */ + intsrcovr->flags =3D cpu_to_le16(1 | (1 << 2)); + } + + for (i =3D x86ms->apic_xrupt_override ? 1 : 0; i < 16; i++) { + intsrcovr =3D acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type =3D ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length =3D sizeof(*intsrcovr); + intsrcovr->source =3D i; + intsrcovr->gsi =3D cpu_to_le32(i); + /* active high, edge triggered */ + intsrcovr->flags =3D cpu_to_le16(1 | (1 << 2)); + } + + if (x86ms->ioapic2) { + for (i =3D 0; i < 16; i++) { + intsrcovr =3D acpi_data_push(table_data, sizeof *intsrcovr= ); + intsrcovr->type =3D ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length =3D sizeof(*intsrcovr); + intsrcovr->source =3D IO_APIC_SECONDARY_IRQBASE + i; + intsrcovr->gsi =3D cpu_to_le32(IO_APIC_SECONDARY_IRQBAS= E + i); + /* active high, edge triggered */ + intsrcovr->flags =3D cpu_to_le16(1 | (1 << 2)); + } + } + } else { + if (x86ms->apic_xrupt_override) { + intsrcovr =3D acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type =3D ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length =3D sizeof(*intsrcovr); + intsrcovr->source =3D 0; + intsrcovr->gsi =3D cpu_to_le32(2); + /* conforms to bus specifications */ + intsrcovr->flags =3D cpu_to_le16(0); + } =20 - for (i =3D 1; i < 16; i++) { - if (!(x86ms->pci_irq_mask & (1 << i))) { - /* No need for a INT source override structure. */ - continue; + for (i =3D 1; i < 16; i++) { + if (!(x86ms->pci_irq_mask & (1 << i))) { + /* No need for a INT source override structure. */ + continue; + } + intsrcovr =3D acpi_data_push(table_data, sizeof *intsrcovr); + intsrcovr->type =3D ACPI_APIC_XRUPT_OVERRIDE; + intsrcovr->length =3D sizeof(*intsrcovr); + intsrcovr->source =3D i; + intsrcovr->gsi =3D cpu_to_le32(i); + /* active high, level triggered */ + intsrcovr->flags =3D cpu_to_le16(0xd); } - intsrcovr =3D acpi_data_push(table_data, sizeof *intsrcovr); - intsrcovr->type =3D ACPI_APIC_XRUPT_OVERRIDE; - intsrcovr->length =3D sizeof(*intsrcovr); - intsrcovr->source =3D i; - intsrcovr->gsi =3D cpu_to_le32(i); - intsrcovr->flags =3D cpu_to_le16(0xd); /* active high, level trig= gered */ } =20 if (x2apic_mode) { --=20 2.25.1