From nobody Fri Dec 19 19:16:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1572047668; cv=none; d=zoho.com; s=zohoarc; b=HOw0rhC89szwBRPoRIB31lMn5XRyPZH5SviQ7QpDpUdU3OR1N98RWKe1XAPAxn41Kfj+qsv/qk1f53aUkG3DYXAFxrQD/pdIcKxhU0YFG5xE/tu7WzbZtzi7EixARQZ/Dbi13jzOfsqSvHmNY5hXQH3qdeyPT6SVfkCSPq0IUsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572047668; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Vtg5uL3NWMvk+judB949v3wF7Dr4vA6K78KvIJYBL7w=; b=M4uuKJEvrlWgGsmiZ/hmy2wYsAWiow2A/kTZ04xsD9KjABpV1iM/2fqyLJomIiLzME/PBSB/TY2g57++eva3BbKyOXgtTAC7ilgpNf9scQf9nCalNs0DrT8WnqjPHoN2mUb2VnBw7HWl9/fe39KIszxxHWXC3vaclZU2lO6If24= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1572047668178873.31690248171; Fri, 25 Oct 2019 16:54:28 -0700 (PDT) Received: from localhost ([::1]:37214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO9PW-00050L-JB for importer@patchew.org; Fri, 25 Oct 2019 19:54:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50145) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO91T-0005ji-4Y for qemu-devel@nongnu.org; Fri, 25 Oct 2019 19:29:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iO91R-0004jO-TX for qemu-devel@nongnu.org; Fri, 25 Oct 2019 19:29:35 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:36814) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iO91R-0004Yx-LU; Fri, 25 Oct 2019 19:29:33 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 26 Oct 2019 07:29:33 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2019 16:24:59 -0700 Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip02.wdc.com with ESMTP; 25 Oct 2019 16:29:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1572046173; x=1603582173; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g37n1ZVkdhVO3F8wxnglbViPKYTuNjM3/io1BWGTgEQ=; b=BbyemCzW2wjELf47Dn6vNobMpGd0Y/8mmBZcFfBjryRL6SoHsjPDhzlp czeZZipSFTwwtV4c6dSUbQC7vPgJcIufnHTzSjj52TEj4stUejFkbUT6v BfhSzDEJLtHhSFc/fUeNia1ZVFbsOTDmqWnXbMlQTR2BpkVpm26k10Hyl cTPsuz9xq1c7q/uS3zna1K8AZUPbp9AMFzLImOWng1HRMFQPR+GHP0Ei6 F5Yh4xG18PoZGuRpgUqC2CqX0UiPUP4lJqbdH070Q7/OFUmodYoJ8pDgi mZyMK+sotnlgw3B4RH+Rk+K5jzyHbZJhPMi4Jyoy5eHEnH+dLLN0CbG5s g==; IronPort-SDR: wqo6lQw/fJqiF6gPo5HVdBqKlK0orCd49QQsSnXbqaLq35eoNnhnTlqnGYfJy9GE1xSnzkja9c 3ssn2a5T8E5LkRg+m56IoE4KbS8EBqdDc3xHYFe7o5Dk/BmyKTkDahTo1XfFWHmZpRuA2/jFE2 46jt95Oz0oO5FHvlI8rKAEuteQxoOebko8ei08VYMIE7BbMP6bfPqgRbrn0aH4YabIsT0n7yPV yLfg5VN6crKXktbOzLrDsOJbZH/Zku9RVxul8szsrlJ9FeTuqH+sTVN0RpuW5rRUfSzrzZwM0I dNY= X-IronPort-AV: E=Sophos;i="5.68,230,1569254400"; d="scan'208";a="122956706" IronPort-SDR: h8IeMF5ZNBhgrkkXD27TJjN86D+0XJsXTTqtvOWwb9HTkY+OgWEE3v2k/aEU/Ops6mxYOMLmS8 qTrgzMx0dboBBe5si1UqtJEF62WGVwSFxb2uWZb+Ls9fu3U8wynupYbtxCv50/srCRLP0uVDWk Fn8r1VoubG+Ok7FpADKhnvR96xFW+HW7NhLZf2F3Wv04iTRBk/X3qAGkIAfynK2r46IH1Mc9IO fng7Sg3PQ5oIh7UPfQcbIyrxGV96394nlq9i3/yCQIEvP6sW0vfPkdtJycixvmfYsHenHp0prW oATz0F69Pi1pgVhSsjUJPAU+ IronPort-SDR: isbioOg7ONCyJlMVGb99z3E9plILh6RClF3WZXFbHVj3yWtVzr0oXeHibQNbNVLCHvia0kFYyP R9cYTRTQ2mgYPEAURcNjYBPvKRC4etBGCufEV468KA22RdFtCF4SFpwwBaPbg5dWrtb97QEqdA XoUeF49hMZHqAl9sMRTU+HrWeoDKz9vzOHqYzBsa/teNRlPnfHFII+Pg4lKr58dsmMHD05X2Pk 9+XfIX52S9jSffMSrzQ+e+PheJfrrBYfeKXbSGeOXb4pDQKi8rPQlZPVXEhCpYVHoHcE21B+vb 2rw= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Date: Fri, 25 Oct 2019 16:24:37 -0700 Message-Id: <70a2a77da9586b6127e7b5405bf1667a31da5fb6.1572045716.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 +++++++++++ target/riscv/cpu_helper.c | 4 ++-- target/riscv/op_helper.c | 2 +- target/riscv/translate.c | 2 +- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a2358c4956..f9389b071d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -365,8 +365,19 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ +#if defined(TARGET_RISCV64) #define MSTATUS_MTL 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#elif defined(TARGET_RISCV32) +#define MSTATUS_MTL 0x00000040 +#define MSTATUS_MPV 0x00000080 +#endif + +#ifdef TARGET_RISCV32 +# define MSTATUS_MPV_ISSET(env) get_field(*env->mstatush, MSTATUS_MPV) +#else +# define MSTATUS_MPV_ISSET(env) get_field(*env->mstatus, MSTATUS_MPV) +#endif =20 #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 79b2f30876..dedca3eea8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -331,7 +331,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, mode =3D get_field(*env->mstatus, MSTATUS_MPP); =20 if (riscv_has_ext(env, RVH) && - get_field(*env->mstatus, MSTATUS_MPV)) { + MSTATUS_MPV_ISSET(env)) { use_background =3D true; } } @@ -718,7 +718,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, m_mode_two_stage =3D env->priv =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(*env->mstatus, MSTATUS_MPRV) && - get_field(*env->mstatus, MSTATUS_MPV); + MSTATUS_MPV_ISSET(env); =20 hs_mode_two_stage =3D env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index a0a631d722..b0b9890a15 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) =20 target_ulong mstatus =3D *env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); - target_ulong prev_virt =3D get_field(mstatus, MSTATUS_MPV); + target_ulong prev_virt =3D MSTATUS_MPV_ISSET(env); mstatus =3D set_field(mstatus, env->priv_ver >=3D PRIV_VERSION_1_10_0 ? MSTATUS_MIE : MSTATUS_UIE << prev_priv, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ea19ba9c5d..f0d9860429 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -754,7 +754,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); if (env->priv_ver =3D=3D PRV_M && get_field(*env->mstatus, MSTATUS_MPRV) && - get_field(*env->mstatus, MSTATUS_MPV)) { + MSTATUS_MPV_ISSET(env)) { ctx->virt_enabled =3D true; } else if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && --=20 2.23.0