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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Arpit Kumar , Jonathan Cameron , Fan Ni , Marcel Apfelbaum Subject: [PULL 27/33] hw/cxl: Add Physical Port Control FMAPI Command (Opcode 5102h) Message-ID: <6e1410fdcf7040b2c32a7845b423ab604384aded.1771770471.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.798, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.79, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1771770914017158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Arpit Kumar Added assert-deassert PERST implementation for physical ports (both USP and DSP's). Assert PERST involves bg operation for holding 100ms. Reset PPB implementation for physical ports. Signed-off-by: Arpit Kumar Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Message-Id: <20260204173223.44122-4-Jonathan.Cameron@huawei.com> --- hw/cxl/cxl-mailbox-utils.c | 130 ++++++++++++++++++++ hw/pci-bridge/cxl_downstream.c | 9 ++ hw/pci-bridge/cxl_upstream.c | 1 + include/hw/cxl/cxl_port.h | 20 +++ include/hw/pci-bridge/cxl_downstream_port.h | 12 ++ include/hw/pci-bridge/cxl_upstream_port.h | 2 + 6 files changed, 174 insertions(+) create mode 100644 include/hw/pci-bridge/cxl_downstream_port.h diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index b6ac987ee0..c83b5f90d4 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -17,6 +17,7 @@ #include "hw/cxl/cxl_mailbox.h" #include "hw/cxl/cxl_port.h" #include "hw/pci/pci.h" +#include "hw/pci-bridge/cxl_downstream_port.h" #include "hw/pci-bridge/cxl_upstream_port.h" #include "qemu/cutils.h" #include "qemu/host-utils.h" @@ -119,6 +120,7 @@ enum { PHYSICAL_SWITCH =3D 0x51, #define IDENTIFY_SWITCH_DEVICE 0x0 #define GET_PHYSICAL_PORT_STATE 0x1 + #define PHYSICAL_PORT_CONTROL 0x2 TUNNEL =3D 0x53, #define MANAGEMENT_COMMAND 0x0 FMAPI_DCD_MGMT =3D 0x56, @@ -616,6 +618,7 @@ static CXLRetCode cmd_get_physical_port_state(const str= uct cxl_cmd *cmd, struct cxl_fmapi_port_state_info_block *port; /* First try to match on downstream port */ PCIDevice *port_dev; + CXLPhyPortPerst *perst; uint16_t lnkcap, lnkcap2, lnksta; =20 port =3D &out->ports[i]; @@ -663,6 +666,7 @@ static CXLRetCode cmd_get_physical_port_state(const str= uct cxl_cmd *cmd, port->supported_cxl_mode_bitmask =3D CXL_PORT_SUPPORTS_68B_VH | CXL_PORT_SUPPORTS_256B; port->supported_ld_count =3D 3; + perst =3D cxl_dsp_get_perst(CXL_DSP(port_dev)); } else if (usp->port =3D=3D in->ports[i]) { /* USP */ port_dev =3D PCI_DEVICE(usp); port->config_state =3D CXL_PORT_CONFIG_STATE_USP; @@ -670,6 +674,7 @@ static CXLRetCode cmd_get_physical_port_state(const str= uct cxl_cmd *cmd, port->connected_device_mode =3D 0; /* Reserved for USP */ port->supported_cxl_mode_bitmask =3D CXL_PORT_SUPPORTS_68B_VH | (CXL_USP(usp)->flitmode ? CXL_PORT_SUPPORTS_256B : 0); + perst =3D &CXL_USP(usp)->perst; } else { return CXL_MBOX_INVALID_INPUT; } @@ -698,6 +703,7 @@ static CXLRetCode cmd_get_physical_port_state(const str= uct cxl_cmd *cmd, /* TODO: Track down if we can get the rest of the info */ port->ltssm_state =3D 0x7; port->first_lane_num =3D 0; + port->link_state =3D perst ? CXL_PORT_LINK_STATE_FLAG_PERST_ASSERT= ED : 0; } =20 pl_size =3D sizeof(*out) + sizeof(*out->ports) * in->num_ports; @@ -706,6 +712,115 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 +static void *bg_assertcb(void *opaque) +{ + CXLPhyPortPerst *perst =3D opaque; + + /* holding reset phase for 100ms */ + while (perst->asrt_time--) { + usleep(1000); + } + perst->issued_assert_perst =3D true; + return NULL; +} + +static CXLRetCode cxl_deassert_perst(Object *obj, CXLPhyPortPerst *perst) +{ + if (!perst->issued_assert_perst) { + return CXL_MBOX_INTERNAL_ERROR; + } + + QEMU_LOCK_GUARD(&perst->lock); + resettable_release_reset(obj, RESET_TYPE_COLD); + perst->issued_assert_perst =3D false; + perst->asrt_time =3D ASSERT_WAIT_TIME_MS; + + return CXL_MBOX_SUCCESS; +} + +static CXLRetCode cxl_assert_perst(Object *obj, CXLPhyPortPerst *perst) +{ + if (cxl_perst_asserted(perst)) { + return CXL_MBOX_INTERNAL_ERROR; + } + + QEMU_LOCK_GUARD(&perst->lock); + resettable_assert_reset(obj, RESET_TYPE_COLD); + qemu_thread_create(&perst->asrt_thread, "assert_thread", bg_assertcb, + perst, QEMU_THREAD_DETACHED); + + return CXL_MBOX_SUCCESS; +} + +static CXLDownstreamPort *cxl_find_dsp_on_bus(PCIBus *bus, uint8_t pn) +{ + + PCIDevice *port_dev =3D pcie_find_port_by_pn(bus, pn); + + if (object_dynamic_cast(OBJECT(port_dev), TYPE_CXL_DSP)) { + return CXL_DSP(port_dev); + } + + return NULL; +} + +/* CXL r3.2 Section 7.6.7.1.3: Get Physical Port Control (Opcode 5102h) */ +static CXLRetCode cmd_physical_port_control(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + CXLPhyPortPerst *perst; + PCIDevice *dev; + + struct cxl_fmapi_get_physical_port_control_req_pl { + uint8_t ppb_id; + uint8_t ports_op; + } QEMU_PACKED *in =3D (void *)payload_in; + + if (len_in < sizeof(*in)) { + return CXL_MBOX_INVALID_PAYLOAD_LENGTH; + } + + if (PCIE_PORT(pp)->port =3D=3D in->ppb_id) { + dev =3D PCI_DEVICE(pp); + perst =3D &pp->perst; + } else { + CXLDownstreamPort *dsp =3D + cxl_find_dsp_on_bus(&PCI_BRIDGE(pp)->sec_bus, in->ppb_id); + + if (!dsp) { + return CXL_MBOX_INVALID_INPUT; + } + dev =3D PCI_DEVICE(dsp); + perst =3D cxl_dsp_get_perst(dsp); + } + + switch (in->ports_op) { + case 0: + return cxl_assert_perst(OBJECT(&dev->qdev), perst); + case 1: + return cxl_deassert_perst(OBJECT(&dev->qdev), perst); + case 2: { + if (!perst) { + return CXL_MBOX_INVALID_INPUT; + } + + if (perst->issued_assert_perst || + perst->asrt_time < ASSERT_WAIT_TIME_MS) { + return CXL_MBOX_INTERNAL_ERROR; + } + device_cold_reset(&dev->qdev); + return CXL_MBOX_SUCCESS; + } + default: + return CXL_MBOX_INVALID_INPUT; + } +} + /* CXL r3.1 Section 8.2.9.1.2: Background Operation Status (Opcode 0002h) = */ static CXLRetCode cmd_infostat_bg_op_sts(const struct cxl_cmd *cmd, uint8_t *payload_in, @@ -4412,6 +4527,8 @@ static const struct cxl_cmd cxl_cmd_set_sw[256][256] = =3D { cmd_identify_switch_device, 0, 0 }, [PHYSICAL_SWITCH][GET_PHYSICAL_PORT_STATE] =3D { "SWITCH_PHYSICAL_PORT= _STATS", cmd_get_physical_port_state, ~0, 0 }, + [PHYSICAL_SWITCH][PHYSICAL_PORT_CONTROL] =3D { "SWITCH_PHYSICAL_PORT_C= ONTROL", + cmd_physical_port_control, 2, 0 }, [TUNNEL][MANAGEMENT_COMMAND] =3D { "TUNNEL_MANAGEMENT_COMMAND", cmd_tunnel_management_cmd, ~0, 0 }, }; @@ -4618,6 +4735,19 @@ static void cxl_rebuild_cel(CXLCCI *cci) } } =20 +void cxl_init_physical_port_control(CXLPhyPortPerst *perst) +{ + qemu_mutex_init(&perst->lock); + perst->issued_assert_perst =3D false; + /* + * Assert PERST involves physical port to be in + * hold reset phase for minimum 100ms. No other + * physical port control requests are entertained + * until Deassert PERST command. + */ + perst->asrt_time =3D ASSERT_WAIT_TIME_MS; +} + void cxl_init_cci(CXLCCI *cci, size_t payload_max) { cci->payload_max =3D payload_max; diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 320818a8f1..ec450d1aa0 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -13,9 +13,11 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" +#include "hw/pci-bridge/cxl_downstream_port.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-properties-system.h" #include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_port.h" #include "qapi/error.h" =20 typedef struct CXLDownstreamPort { @@ -24,6 +26,7 @@ typedef struct CXLDownstreamPort { =20 /*< public >*/ CXLComponentState cxl_cstate; + CXLPhyPortPerst perst; } CXLDownstreamPort; =20 #define CXL_DOWNSTREAM_PORT_MSI_OFFSET 0x70 @@ -81,6 +84,11 @@ static void cxl_dsp_config_write(PCIDevice *d, uint32_t = address, cxl_dsp_dvsec_write_config(d, address, val, len); } =20 +CXLPhyPortPerst *cxl_dsp_get_perst(CXLDownstreamPort *dsp) +{ + return &dsp->perst; +} + static void cxl_dsp_reset(DeviceState *qdev) { PCIDevice *d =3D PCI_DEVICE(qdev); @@ -92,6 +100,7 @@ static void cxl_dsp_reset(DeviceState *qdev) pci_bridge_reset(qdev); =20 latch_registers(dsp); + cxl_init_physical_port_control(&dsp->perst); } =20 static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index fb8d19539c..b6281cbd4c 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -103,6 +103,7 @@ static void cxl_usp_reset(DeviceState *qdev) pcie_cap_deverr_reset(d); pcie_cap_fill_link_ep_usp(d, usp->width, usp->speed, usp->flitmode); latch_registers(usp); + cxl_init_physical_port_control(&usp->perst); } =20 static void build_dvsecs(CXLUpstreamPort *usp) diff --git a/include/hw/cxl/cxl_port.h b/include/hw/cxl/cxl_port.h index 04db60f7bc..fb2e22a9f2 100644 --- a/include/hw/cxl/cxl_port.h +++ b/include/hw/cxl/cxl_port.h @@ -3,6 +3,8 @@ #ifndef CXL_PORT_H #define CXL_PORT_H =20 +#include "qemu/thread.h" + /* CXL r3.2 Table 7-19: Get Physical Port State Port Information Block For= mat */ #define CXL_PORT_CONFIG_STATE_DISABLED 0x0 #define CXL_PORT_CONFIG_STATE_BIND_IN_PROGRESS 0x1 @@ -50,4 +52,22 @@ #define CXL_PORT_LINK_STATE_FLAG_PRSNT BIT(2) #define CXL_PORT_LINK_STATE_FLAG_POWER_OFF BIT(3) =20 +#define CXL_MAX_PHY_PORTS 256 +#define ASSERT_WAIT_TIME_MS 100 /* Assert - Deassert PERST */ + +/* Assert - Deassert PERST */ +typedef struct CXLPhyPortPerst { + bool issued_assert_perst; + QemuMutex lock; /* protecting assert-deassert reset request */ + uint64_t asrt_time; + QemuThread asrt_thread; /* thread for 100ms delay */ +} CXLPhyPortPerst; + +void cxl_init_physical_port_control(CXLPhyPortPerst *perst); + +static inline bool cxl_perst_asserted(CXLPhyPortPerst *perst) +{ + return perst->issued_assert_perst || perst->asrt_time < ASSERT_WAIT_TI= ME_MS; +} + #endif /* CXL_PORT_H */ diff --git a/include/hw/pci-bridge/cxl_downstream_port.h b/include/hw/pci-b= ridge/cxl_downstream_port.h new file mode 100644 index 0000000000..1611504c87 --- /dev/null +++ b/include/hw/pci-bridge/cxl_downstream_port.h @@ -0,0 +1,12 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef CXL_DOWNSTREAM_PORT_H +#define CXL_DOWNSTREAM_PORT_H +#include "include/hw/cxl/cxl_port.h" + +typedef struct CXLDownstreamPort CXLDownstreamPort; +CXLPhyPortPerst *cxl_dsp_get_perst(CXLDownstreamPort *dsp); + +#endif diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bri= dge/cxl_upstream_port.h index e3d6a27acc..dfe01771c7 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -4,6 +4,7 @@ #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" #include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_port.h" =20 typedef struct CXLUpstreamPort { /*< private >*/ @@ -12,6 +13,7 @@ typedef struct CXLUpstreamPort { /*< public >*/ CXLComponentState cxl_cstate; CXLCCI swcci; + CXLPhyPortPerst perst; =20 PCIExpLinkSpeed speed; PCIExpLinkWidth width; --=20 MST