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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 6 ++--- target/riscv/cpu_helper.c | 52 ++++++++++++++++++++------------------- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6096243aed..8bde15544d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -194,9 +194,8 @@ struct CPURISCVState { target_ulong vscause; target_ulong vstval; target_ulong vsatp; -#ifdef TARGET_RISCV32 + /* This is RV32 only */ target_ulong vsstatush; -#endif =20 target_ulong mtval2; target_ulong mtinst; @@ -209,9 +208,8 @@ struct CPURISCVState { target_ulong stval_hs; target_ulong satp_hs; target_ulong mstatus_hs; -#ifdef TARGET_RISCV32 + /* This is RV32 only */ target_ulong mstatush_hs; -#endif =20 target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4652082df1..62aed24feb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -126,10 +126,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *en= v) env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->mstatus_hs; =20 -#if defined(TARGET_RISCV32) - env->vsstatush =3D env->mstatush; - env->mstatush |=3D env->mstatush_hs; -#endif + if (riscv_cpu_is_32bit(env)) { + env->vsstatush =3D env->mstatush; + env->mstatush |=3D env->mstatush_hs; + } =20 env->vstvec =3D env->stvec; env->stvec =3D env->stvec_hs; @@ -154,10 +154,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *en= v) env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->vsstatus; =20 -#if defined(TARGET_RISCV32) - env->mstatush_hs =3D env->mstatush; - env->mstatush |=3D env->vsstatush; -#endif + if (riscv_cpu_is_32bit(env)) { + env->mstatush_hs =3D env->mstatush; + env->mstatush |=3D env->vsstatush; + } =20 env->stvec_hs =3D env->stvec; env->stvec =3D env->vstvec; @@ -472,11 +472,13 @@ restart: return TRANSLATE_PMP_FAIL; } =20 -#if defined(TARGET_RISCV32) - target_ulong pte =3D address_space_ldl(cs->as, pte_addr, attrs, &r= es); -#elif defined(TARGET_RISCV64) - target_ulong pte =3D address_space_ldq(cs->as, pte_addr, attrs, &r= es); -#endif + target_ulong pte; + if (riscv_cpu_is_32bit(env)) { + pte =3D address_space_ldl(cs->as, pte_addr, attrs, &res); + } else { + pte =3D address_space_ldq(cs->as, pte_addr, attrs, &res); + } + if (res !=3D MEMTX_OK) { return TRANSLATE_FAIL; } @@ -995,19 +997,19 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env)) { riscv_cpu_swap_hypervisor_regs(env); } -#ifdef TARGET_RISCV32 - env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatush =3D set_field(env->mstatush, MSTATUS_GVA, 1); - } -#else - env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); + if (riscv_cpu_is_32bit(env)) { + env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatush =3D set_field(env->mstatush, MSTATUS_GVA= , 1); + } + } else { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, = 1); + } } -#endif =20 mtval2 =3D env->guest_phys_fault_addr; =20 --=20 2.28.0