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X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 03/23] target/riscv: Add the virtulisation mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu_bits.h | 6 ++++++ target/riscv/cpu_helper.c | 23 +++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3337d1aef3..de4843b879 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -132,6 +132,8 @@ struct CPURISCVState { =20 #ifndef CONFIG_USER_ONLY target_ulong priv; + /* This contains QEMU specific information about the virt state. */ + target_ulong virt; target_ulong resetvec; =20 target_ulong mhartid; @@ -278,6 +280,8 @@ void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +bool riscv_cpu_virt_enabled(CPURISCVState *env); +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dc9d53d4be..07c95e8d2c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -417,6 +417,12 @@ #define PRV_H 2 /* Reserved */ #define PRV_M 3 =20 +/* Virtulisation modes */ +#define VIRT_OFF 0 +#define VIRT_ON 1 +#define VIRT_MODE_SHIFT 0 +#define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT) + /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7fc00000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 872835177a..5912ae63b7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,6 +71,29 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 #if !defined(CONFIG_USER_ONLY) =20 +bool riscv_cpu_virt_enabled(CPURISCVState *env) +{ + bool tmp; + + if (!riscv_has_ext(env, RVH)) { + return false; + } + + tmp =3D (env->virt & VIRT_MODE_MASK) >> VIRT_MODE_SHIFT; + + return tmp =3D=3D VIRT_ON; +} + +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt &=3D ~VIRT_MODE_MASK; + env->virt |=3D enable << VIRT_MODE_SHIFT; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; --=20 2.21.0