From nobody Mon Feb 9 10:57:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1609802941; cv=none; d=zohomail.com; s=zohoarc; b=JSVDNfFMvWvUgOX3KEqx9/Qxh4C1MO7JCp5wTg06CwmFDZ7qFBk2rbYmw+2ayDT21stWjpTlnSXldDBuBZ2Em4/w6QnYF6eareIsZok3T9QY0m1IgRD82TTOwobJ0BWhF76EDWzBR/2GapZc9HBG/Spawvd114N0zdLG3BeU1Y8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609802941; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=dtQl/uR/XcD3BamnsDKg6RLLHpaA3zE9C784JyGp6bc=; b=C5TdIQ3FlYj9X8J9+WL6bIY7aA2waEOjtd0vacv/020aGr+Zc5+96uegsm6m84yPey9QEnU/xMqsbZ4orf4XoO0GBTo2y4jw65w245AXDBeq5+RMSCYjaxm9tp+WwU2urjsGDNkq8rzVuaQX50XM0YuCgtnw6bUywDjGqh1XbSU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1609802941718723.0643384669758; Mon, 4 Jan 2021 15:29:01 -0800 (PST) Received: from localhost ([::1]:43848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kwZHY-0002Yk-Jg for importer@patchew.org; Mon, 04 Jan 2021 18:29:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwZCC-00066I-8f; Mon, 04 Jan 2021 18:23:28 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:55669) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwZC7-0007ym-P4; Mon, 04 Jan 2021 18:23:28 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A4D7B7470F0; Tue, 5 Jan 2021 00:23:20 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 1C6257470DF; Tue, 5 Jan 2021 00:23:20 +0100 (CET) Message-Id: <6a97eaad3faf7fe5c998f6e8953f6b851cf8757e.1609802040.git.balaton@eik.bme.hu> In-Reply-To: References: Subject: [PATCH v4 3/4] ppc440_pcix: Fix up pci config access Date: Tue, 05 Jan 2021 00:14:00 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , f4bug@amsat.org, Guenter Roeck , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: BALATON Zoltan From: BALATON Zoltan via Content-Type: text/plain; charset="utf-8" This fixes a long standing issue with MorphOS booting on sam460ex which turns out to be because of suspicious values written to PCI config address that apparently works on real machine but caused wrong access on this device model. This replaces a previous work around for this with a better fix that makes it work. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_pcix.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index 7829d3e556..91cbcd0504 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -449,28 +449,35 @@ static AddressSpace *ppc440_pcix_set_iommu(PCIBus *b,= void *opaque, int devfn) return &s->bm_as; } =20 -/* The default pci_host_data_{read,write} functions in pci/pci_host.c - * deny access to registers without bit 31 set but our clients want - * this to work so we have to override these here */ -static void pci_host_data_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) +/* + * Some guests on sam460ex write all kinds of garbage here such as + * missing enable bit and low bits set and still expect this to work + * (apparently it does on real hardware because these boot there) so + * we have to override these ops here and fix it up + */ +static void pci_host_config_write(void *opaque, hwaddr addr, + uint64_t val, unsigned len) { PCIHostState *s =3D opaque; - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); + + if (addr !=3D 0 || len !=3D 4) { + return; + } + s->config_reg =3D (val & 0xfffffffcULL) | (1UL << 31); } =20 -static uint64_t pci_host_data_read(void *opaque, - hwaddr addr, unsigned len) +static uint64_t pci_host_config_read(void *opaque, hwaddr addr, + unsigned len) { PCIHostState *s =3D opaque; - uint32_t val; - val =3D pci_data_read(s->bus, s->config_reg | (addr & 3), len); + uint32_t val =3D s->config_reg; + return val; } =20 -const MemoryRegionOps ppc440_pcix_host_data_ops =3D { - .read =3D pci_host_data_read, - .write =3D pci_host_data_write, +const MemoryRegionOps ppc440_pcix_host_conf_ops =3D { + .read =3D pci_host_config_read, + .write =3D pci_host_config_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 @@ -497,9 +504,9 @@ static void ppc440_pcix_realize(DeviceState *dev, Error= **errp) pci_setup_iommu(h->bus, ppc440_pcix_set_iommu, s); =20 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_= SIZE); - memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, + memory_region_init_io(&h->conf_mem, OBJECT(s), &ppc440_pcix_host_conf_= ops, h, "pci-conf-idx", 4); - memory_region_init_io(&h->data_mem, OBJECT(s), &ppc440_pcix_host_data_= ops, + memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h, "pci-conf-data", 4); memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s, "pci.reg", PPC440_REG_SIZE); --=20 2.21.3