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Tsirkin" , marcel.apfelbaum@gmail.com, fam@euphon.net, kwolf@redhat.com, stefanha@redhat.com, k.jensen@samsung.com, f4bug@amsat.org, its@irrelevant.dk, xypron.glpk@gmx.de, imammedo@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com, kbusch@kernel.org, hreitz@redhat.com, ani@anisinha.ca X-Mailer: Apple Mail (2.3608.120.23.2.1) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=wlfightup@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1660832787361100001 Content-Type: text/plain; charset="utf-8" If it is a pcie device, check that all devices on the path from the device to the root complex have ACS enabled, and then the device will become an iommu_group. pci_acs_path_enabled, this function in the Linux kernel, it means that if the device is a PCIe device, check the path from the device to the root complex. If ACS is all enabled, the device will become an iommu_group. acs determine whether it is a separate iommu_group. Signed-off-by: wlfightup =E2=80=94 v3: - Suggested by Michael S. Tsirkin, use x-disable-acs, and set the default value to true, Compatible with previous defaults v2: - Allow ACS to be disabled. - Suggested by Michael S. Tsirkin, use disable-acs to set property. hw/pci-bridge/xio3130_upstream.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstr= eam.c index 5ff46ef050..f918113d76 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -24,6 +24,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "qemu/module.h" @@ -37,6 +38,8 @@ #define XIO3130_SSVID_SSID 0 #define XIO3130_EXP_OFFSET 0x90 #define XIO3130_AER_OFFSET 0x100 +#define XIO3130_ACS_OFFSET \ + (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF) static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) @@ -57,6 +60,7 @@ static void xio3130_upstream_reset(DeviceState *qdev) static void xio3130_upstream_realize(PCIDevice *d, Error **errp) { PCIEPort *p =3D PCIE_PORT(d); + PCIESlot *s =3D PCIE_SLOT(d); int rc; pci_bridge_initfn(d, TYPE_PCIE_BUS); @@ -92,6 +96,9 @@ static void xio3130_upstream_realize(PCIDevice *d, Error = **errp) goto err; } + if (!s->disable_acs) { + pcie_acs_init(d, XIO3130_ACS_OFFSET); + } return; err: @@ -110,6 +117,11 @@ static void xio3130_upstream_exitfn(PCIDevice *d) pci_bridge_exitfn(d); } +static Property xio3130_upstream_props[] =3D { + DEFINE_PROP_BOOL("x-disable-acs", PCIESlot, disable_acs, true), + DEFINE_PROP_END_OF_LIST() +}; + static const VMStateDescription vmstate_xio3130_upstream =3D { .name =3D "xio3130-express-upstream-port", .priority =3D MIG_PRI_PCI_BUS, @@ -139,6 +151,7 @@ static void xio3130_upstream_class_init(ObjectClass *kl= ass, void *data) dc->desc =3D "TI X3130 Upstream Port of PCI Express Switch"; dc->reset =3D xio3130_upstream_reset; dc->vmsd =3D &vmstate_xio3130_upstream; + device_class_set_props(dc, xio3130_upstream_props); } static const TypeInfo xio3130_upstream_info =3D { --=20 2.24.3 (Apple Git-128)