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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=703660e7d=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 44 ++++++++++++++++++++------------------- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 4 ++-- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index caf4599207..8ae404c32a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -527,27 +527,29 @@ #define DEFAULT_RSTVEC 0x1000 =20 /* Exception causes */ -#define EXCP_NONE -1 /* sentinel value */ -#define RISCV_EXCP_INST_ADDR_MIS 0x0 -#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 -#define RISCV_EXCP_ILLEGAL_INST 0x2 -#define RISCV_EXCP_BREAKPOINT 0x3 -#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 -#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 -#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 -#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 -#define RISCV_EXCP_U_ECALL 0x8 -#define RISCV_EXCP_S_ECALL 0x9 -#define RISCV_EXCP_VS_ECALL 0xa -#define RISCV_EXCP_M_ECALL 0xb -#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0= */ -#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0= */ -#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0= */ -#define RISCV_EXCP_SEMIHOST 0x10 -#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 -#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 -#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 -#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 +typedef enum RiscVException { + RISCV_EXCP_NONE =3D -1, /* sentinel value */ + RISCV_EXCP_INST_ADDR_MIS =3D 0x0, + RISCV_EXCP_INST_ACCESS_FAULT =3D 0x1, + RISCV_EXCP_ILLEGAL_INST =3D 0x2, + RISCV_EXCP_BREAKPOINT =3D 0x3, + RISCV_EXCP_LOAD_ADDR_MIS =3D 0x4, + RISCV_EXCP_LOAD_ACCESS_FAULT =3D 0x5, + RISCV_EXCP_STORE_AMO_ADDR_MIS =3D 0x6, + RISCV_EXCP_STORE_AMO_ACCESS_FAULT =3D 0x7, + RISCV_EXCP_U_ECALL =3D 0x8, + RISCV_EXCP_S_ECALL =3D 0x9, + RISCV_EXCP_VS_ECALL =3D 0xa, + RISCV_EXCP_M_ECALL =3D 0xb, + RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ + RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ + RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SEMIHOST =3D 0x10, + RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, + RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT =3D 0x15, + RISCV_EXCP_VIRT_INSTRUCTION_FAULT =3D 0x16, + RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT =3D 0x17, +} RiscVException; =20 #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2a990f6253..63584b4a20 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -357,7 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mcause =3D 0; env->pc =3D env->resetvec; #endif - cs->exception_index =3D EXCP_NONE; + cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 83a6bcfad0..af702f65b1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) if (irqs) { return ctz64(irqs); /* since non-zero */ } else { - return EXCP_NONE; /* indicates no pending interrupt */ + return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } #endif @@ -1017,5 +1017,5 @@ void riscv_cpu_do_interrupt(CPUState *cs) */ =20 #endif - cs->exception_index =3D EXCP_NONE; /* mark handled to qemu */ + cs->exception_index =3D RISCV_EXCP_NONE; /* mark handled to qemu */ } --=20 2.30.1