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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=703660e7d=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 11 +++++++---- target/riscv/csr.c | 37 ++++++++++++++++++------------------- target/riscv/gdbstub.c | 8 ++++---- target/riscv/op_helper.c | 18 +++++++++--------- 4 files changed, 38 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7af9fff776..179685d07b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -451,10 +451,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, *pflags =3D flags; } =20 -int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask); -int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_val= ue, - target_ulong new_value, target_ulong write_mask); +RiscVException riscv_csrrw(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask= ); +RiscVException riscv_csrrw_debug(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask); =20 static inline void riscv_csr_write(CPURISCVState *env, int csrno, target_ulong val) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 61b2abdc14..fbe38dd261 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1404,10 +1404,11 @@ static RiscVException write_pmpaddr(CPURISCVState *= env, int csrno, * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); */ =20 -int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) +RiscVException riscv_csrrw(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) { - int ret; + RiscVException ret; target_ulong old_value; RISCVCPU *cpu =3D env_archcpu(env); =20 @@ -1429,41 +1430,37 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, =20 if ((write_mask && read_only) || (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } #endif =20 /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } =20 /* check predicate */ if (!csr_ops[csrno].predicate) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } ret =3D csr_ops[csrno].predicate(env, csrno); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } =20 /* execute combined read/write operation if it exists */ if (csr_ops[csrno].op) { - ret =3D csr_ops[csrno].op(env, csrno, ret_value, new_value, write_= mask); - if (ret !=3D RISCV_EXCP_NONE) { - return -ret; - } - return 0; + return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_m= ask); } =20 /* if no accessor exists then return failure */ if (!csr_ops[csrno].read) { - return -RISCV_EXCP_ILLEGAL_INST; + return RISCV_EXCP_ILLEGAL_INST; } /* read old value */ ret =3D csr_ops[csrno].read(env, csrno, &old_value); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } =20 /* write value if writable and write mask set, otherwise drop writes */ @@ -1472,7 +1469,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, if (csr_ops[csrno].write) { ret =3D csr_ops[csrno].write(env, csrno, new_value); if (ret !=3D RISCV_EXCP_NONE) { - return -ret; + return ret; } } } @@ -1482,17 +1479,19 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, *ret_value =3D old_value; } =20 - return 0; + return RISCV_EXCP_NONE; } =20 /* * Debugger support. If not in user mode, set env->debugger before the * riscv_csrrw call and clear it after the call. */ -int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_val= ue, - target_ulong new_value, target_ulong write_mask) +RiscVException riscv_csrrw_debug(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask) { - int ret; + RiscVException ret; #if !defined(CONFIG_USER_ONLY) env->debugger =3D true; #endif diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5f96b7ea2a..fdc51ea165 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -71,7 +71,7 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArr= ay *buf, int n) */ result =3D riscv_csrrw_debug(env, n - 32, &val, 0, 0); - if (result =3D=3D 0) { + if (result !=3D RISCV_EXCP_NONE) { return gdb_get_regl(buf, val); } } @@ -94,7 +94,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t = *mem_buf, int n) */ result =3D riscv_csrrw_debug(env, n - 32, NULL, val, -1); - if (result =3D=3D 0) { + if (result !=3D RISCV_EXCP_NONE) { return sizeof(target_ulong); } } @@ -108,7 +108,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteA= rray *buf, int n) int result; =20 result =3D riscv_csrrw_debug(env, n, &val, 0, 0); - if (result =3D=3D 0) { + if (result !=3D RISCV_EXCP_NONE) { return gdb_get_regl(buf, val); } } @@ -122,7 +122,7 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_= t *mem_buf, int n) int result; =20 result =3D riscv_csrrw_debug(env, n, NULL, val, -1); - if (result =3D=3D 0) { + if (result !=3D RISCV_EXCP_NONE) { return sizeof(target_ulong); } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eddcb94de..c84b9f8557 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -42,10 +42,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ul= ong src, target_ulong csr) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, src, -1); + RiscVException ret =3D riscv_csrrw(env, csr, &val, src, -1); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); } return val; } @@ -54,10 +54,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ul= ong src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0); + RiscVException ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src = : 0); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); } return val; } @@ -66,10 +66,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ul= ong src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - int ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0); + RiscVException ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src := 0); =20 - if (ret < 0) { - riscv_raise_exception(env, -ret, GETPC()); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); } return val; } --=20 2.30.1