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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=dan.j.williams@intel.com; helo=mgamail.intel.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.365, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1709745433924100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" [ add Li Ming ] Jonathan Cameron wrote: [..] > Robert / Terry, I tracked down the patch where you enabled this for RCHs = and there was > some discussion on walking out on VH as well to enable this, but seems it > never happened. Can you remember why? Just kicked back for a future occa= sion? >=20 Li Ming has this patch below waiting in wings. Li Ming, this patch is timely for this dicussion, care to send out the full series? I expect it needs to be an RFC given concerns with integrating with the pending port switch error handling work. -- 8< -- From: Li Ming Subject: [PATCH RFC v3 3/6] PCI/AER: Enable RCEC to report internal error f= or CXL root port Date: Thu, 1 Feb 2024 05:58:08 +0000 Per CXL r3.1 section 12.2.2, RCEC is possible to log the CXL.cachemem protocol errors detected by CXL root port as PCI_ERR_UNC_INTN or PCI_ERR_COR_INTERNAL in AER Capability. So unmask PCI_ERR_UNC_INTN and PCI_ERR_COR_INTERNAL for that case. Signed-off-by: Li Ming --- drivers/pci/pcie/aer.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 42a3bd35a3e1..ef8fd77cb920 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -985,7 +985,7 @@ static bool cxl_error_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); =20 - return (pcie_ports_native || host->native_aer); + return (pcie_ports_native || host->native_aer) && host->is_cxl; } =20 static bool is_internal_error(struct aer_err_info *info) @@ -1041,8 +1041,14 @@ static int handles_cxl_error_iter(struct pci_dev *de= v, void *data) { bool *handles_cxl =3D data; =20 - if (!*handles_cxl) - *handles_cxl =3D is_cxl_mem_dev(dev) && cxl_error_is_native(dev); + if (!*handles_cxl) { + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_END && + is_cxl_mem_dev(dev) && cxl_error_is_native(dev)) + *handles_cxl =3D true; + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT && + cxl_error_is_native(dev)) + *handles_cxl =3D true; + } =20 /* Non-zero terminates iteration */ return *handles_cxl; @@ -1054,13 +1060,18 @@ static bool handles_cxl_errors(struct pci_dev *rcec) =20 if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + pcie_walk_rcec_all(rcec, handles_cxl_error_iter, &handles_cxl); =20 return handles_cxl; } =20 -static void cxl_rch_enable_rcec(struct pci_dev *rcec) +static void cxl_enable_rcec(struct pci_dev *rcec) { + /* + * Enable RCEC's internal error report for two cases: + * 1. RCiEP detected CXL.cachemem protocol errors + * 2. CXL root port detected CXL.cachemem protocol errors. + */ if (!handles_cxl_errors(rcec)) return; =20 @@ -1069,7 +1080,7 @@ static void cxl_rch_enable_rcec(struct pci_dev *rcec) } =20 #else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } +static inline void cxl_enable_rcec(struct pci_dev *dev) { } static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } #endif @@ -1494,7 +1505,7 @@ static int aer_probe(struct pcie_device *dev) return status; } =20 - cxl_rch_enable_rcec(port); + cxl_enable_rcec(port); aer_enable_rootport(rpc); pci_info(port, "enabled with IRQ %d\n", dev->irq); return 0; --=20 2.40.1