From nobody Sat Feb 7 06:54:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1528071906905736.0655871239195; Sun, 3 Jun 2018 17:25:06 -0700 (PDT) Received: from localhost ([::1]:37028 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fPdIx-0005nT-Eu for importer@patchew.org; Sun, 03 Jun 2018 20:24:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fPdGq-0004bV-0V for qemu-devel@nongnu.org; Sun, 03 Jun 2018 20:22:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fPdGo-0008Gq-Om for qemu-devel@nongnu.org; Sun, 03 Jun 2018 20:22:48 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:38626) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fPdGo-0008FR-HJ; Sun, 03 Jun 2018 20:22:46 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A083374569D; Mon, 4 Jun 2018 02:22:39 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 9CDB57456A0; Mon, 4 Jun 2018 02:22:32 +0200 (CEST) Message-Id: <63c008337021769f6e207d5bbe7c576b99586ec2.1528069840.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Mon, 04 Jun 2018 01:50:40 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH 4/4] sm501: Do not clear read only bits when writing register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When writing a register that has read only bits besides reserved bits we have to avoid changing read only bits that may have non zero default values. While at it, fix a reserved bit mask and a white space error. Signed-off-by: BALATON Zoltan --- hw/display/sm501.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index f4bb33c..51b2bb8 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -837,10 +837,10 @@ static void sm501_system_config_write(void *opaque, h= waddr addr, =20 switch (addr) { case SM501_SYSTEM_CONTROL: - s->system_control =3D value & 0xE300B8F7; + s->system_control |=3D value & 0xEF00B8F7; break; case SM501_MISC_CONTROL: - s->misc_control =3D value & 0xFF7FFF20; + s->misc_control |=3D value & 0xFF7FFF10; break; case SM501_GPIO31_0_CONTROL: s->gpio_31_0_control =3D value; @@ -854,7 +854,7 @@ static void sm501_system_config_write(void *opaque, hwa= ddr addr, s->dram_control |=3D value & 0x7FFFFFC3; break; case SM501_ARBTRTN_CONTROL: - s->arbitration_control =3D value & 0x37777777; + s->arbitration_control =3D value & 0x37777777; break; case SM501_IRQ_MASK: s->irq_mask =3D value; --=20 2.7.6