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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Sairaj Kodilkar , Vasant Hegde , Alejandro Jimenez , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL 03/14] amd_iommu: Support 64-bit address for IOTLB lookup Message-ID: <637dc49a3ae6b72cdb6415dcdcdb22ff770f2c8d.1762698873.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1762699003086158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sairaj Kodilkar The physical AMD IOMMU supports up to 64 bits of IOVA. When a device tries to read or write from a given DMA address, the IOMMU translates the address using the I/O page tables assigned to that device. Since the emulated IOMMU uses per-device page tables, an ideal cache tag would need to be 68 bits (64-bit address - 12-bit page alignment + 16-bit device ID). The current software IOTLB implementation uses a GLib hash table with a 64-bit key to hash both the IOVA and device ID, which limits the IOVA to 60 bits. This causes a failure while setting up the device when a guest is booted with "iommu.forcedac=3D1", which forces the use of DMA addresses at = the top of the 64-bit address space. To address this issue, construct the 64-bit hash key using the upper 52 bits of IOVA (GFN) and lower 12 bits of the device ID to avoid truncation as much as possible (reducing hash collisions). Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU") Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde Reviewed-by: Alejandro Jimenez Tested-by: Alejandro Jimenez Signed-off-by: Alejandro Jimenez Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Message-Id: <20251103203209.645434-4-alejandro.j.jimenez@oracle.com> --- hw/i386/amd_iommu.h | 4 ++-- hw/i386/amd_iommu.c | 57 ++++++++++++++++++++++++++++++--------------- 2 files changed, 40 insertions(+), 21 deletions(-) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 38471b95d1..302ccca512 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -220,8 +220,8 @@ #define PAGE_SIZE_PTE_COUNT(pgsz) (1ULL << ((ctz64(pgsz) - 12) % 9)) =20 /* IOTLB */ -#define AMDVI_IOTLB_MAX_SIZE 1024 -#define AMDVI_DEVID_SHIFT 36 +#define AMDVI_IOTLB_MAX_SIZE 1024 +#define AMDVI_GET_IOTLB_GFN(addr) (addr >> AMDVI_PAGE_SHIFT_4K) =20 /* default extended feature */ #define AMDVI_DEFAULT_EXT_FEATURES \ diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 5c5cfd4989..d689a06eca 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -106,6 +106,11 @@ typedef struct AMDVIAsKey { uint8_t devfn; } AMDVIAsKey; =20 +typedef struct AMDVIIOTLBKey { + uint64_t gfn; + uint16_t devid; +} AMDVIIOTLBKey; + uint64_t amdvi_extended_feature_register(AMDVIState *s) { uint64_t feature =3D AMDVI_DEFAULT_EXT_FEATURES; @@ -377,16 +382,6 @@ static void amdvi_log_pagetab_error(AMDVIState *s, uin= t16_t devid, PCI_STATUS_SIG_TARGET_ABORT); } =20 -static gboolean amdvi_uint64_equal(gconstpointer v1, gconstpointer v2) -{ - return *((const uint64_t *)v1) =3D=3D *((const uint64_t *)v2); -} - -static guint amdvi_uint64_hash(gconstpointer v) -{ - return (guint)*(const uint64_t *)v; -} - static gboolean amdvi_as_equal(gconstpointer v1, gconstpointer v2) { const AMDVIAsKey *key1 =3D v1; @@ -425,11 +420,30 @@ static AMDVIAddressSpace *amdvi_get_as_by_devid(AMDVI= State *s, uint16_t devid) amdvi_find_as_by_devid, &devid); } =20 +static gboolean amdvi_iotlb_equal(gconstpointer v1, gconstpointer v2) +{ + const AMDVIIOTLBKey *key1 =3D v1; + const AMDVIIOTLBKey *key2 =3D v2; + + return key1->devid =3D=3D key2->devid && key1->gfn =3D=3D key2->gfn; +} + +static guint amdvi_iotlb_hash(gconstpointer v) +{ + const AMDVIIOTLBKey *key =3D v; + /* Use GPA and DEVID to find the bucket */ + return (guint)(key->gfn << AMDVI_PAGE_SHIFT_4K | + (key->devid & ~AMDVI_PAGE_MASK_4K)); +} + + static AMDVIIOTLBEntry *amdvi_iotlb_lookup(AMDVIState *s, hwaddr addr, uint64_t devid) { - uint64_t key =3D (addr >> AMDVI_PAGE_SHIFT_4K) | - ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); + AMDVIIOTLBKey key =3D { + .gfn =3D AMDVI_GET_IOTLB_GFN(addr), + .devid =3D devid, + }; return g_hash_table_lookup(s->iotlb, &key); } =20 @@ -451,8 +465,10 @@ static gboolean amdvi_iotlb_remove_by_devid(gpointer k= ey, gpointer value, static void amdvi_iotlb_remove_page(AMDVIState *s, hwaddr addr, uint64_t devid) { - uint64_t key =3D (addr >> AMDVI_PAGE_SHIFT_4K) | - ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); + AMDVIIOTLBKey key =3D { + .gfn =3D AMDVI_GET_IOTLB_GFN(addr), + .devid =3D devid, + }; g_hash_table_remove(s->iotlb, &key); } =20 @@ -463,8 +479,10 @@ static void amdvi_update_iotlb(AMDVIState *s, uint16_t= devid, /* don't cache erroneous translations */ if (to_cache.perm !=3D IOMMU_NONE) { AMDVIIOTLBEntry *entry =3D g_new(AMDVIIOTLBEntry, 1); - uint64_t *key =3D g_new(uint64_t, 1); - uint64_t gfn =3D gpa >> AMDVI_PAGE_SHIFT_4K; + AMDVIIOTLBKey *key =3D g_new(AMDVIIOTLBKey, 1); + + key->gfn =3D AMDVI_GET_IOTLB_GFN(gpa); + key->devid =3D devid; =20 trace_amdvi_cache_update(domid, PCI_BUS_NUM(devid), PCI_SLOT(devid= ), PCI_FUNC(devid), gpa, to_cache.translated_addr); @@ -477,7 +495,8 @@ static void amdvi_update_iotlb(AMDVIState *s, uint16_t = devid, entry->perms =3D to_cache.perm; entry->translated_addr =3D to_cache.translated_addr; entry->page_mask =3D to_cache.addr_mask; - *key =3D gfn | ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); + entry->devid =3D devid; + g_hash_table_replace(s->iotlb, key, entry); } } @@ -2526,8 +2545,8 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) } } =20 - s->iotlb =3D g_hash_table_new_full(amdvi_uint64_hash, - amdvi_uint64_equal, g_free, g_free); + s->iotlb =3D g_hash_table_new_full(amdvi_iotlb_hash, + amdvi_iotlb_equal, g_free, g_free); =20 s->address_spaces =3D g_hash_table_new_full(amdvi_as_hash, amdvi_as_equal, g_free, g_free); --=20 MST