From nobody Tue Feb 10 08:04:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697185403; cv=none; d=zohomail.com; s=zohoarc; b=hCohyKKbJYLQKU7UdyWV2SgVSROSrWQPLmt4rVV1ti1aT1ao89pv8H0sgRxvk1SQCYt+aWQ43gspujMOKCbZyI1A9wYqn1MRZY+H5PRz49MGCcOa6lfGZIyNx4Cl6AzT3HX0E49ToLcI0P0lYX94SQhckDoas83Fj1aH+2Jm0kw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697185403; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=a7CRH59E7WDah93GOZUBpOMCM1LCjMQKDPJEI6Vj50o=; b=FtGGpeId0cU59jdLS/mfek1FxwoTFS7ydM1ZsWkoybO2RIxsUeZJpEGpi2WrOmtNsIk0obxY9cpVpKvEFRReIjev2PX3Se4lcKUhVQQ0s38ZVOacXLU4B4EwiWTeiGE5JoCd+gnhaUA+Iw8PDVeQWlK+AUR189N8vXxNEi0LBdk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697185403911565.3034956260565; Fri, 13 Oct 2023 01:23:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrCz4-0004YQ-Gf; Fri, 13 Oct 2023 03:53:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qrCxu-0001It-UI for qemu-devel@nongnu.org; Fri, 13 Oct 2023 03:52:11 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qrCxa-0005G6-9I for qemu-devel@nongnu.org; Fri, 13 Oct 2023 03:52:10 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40537481094so19559795e9.0 for ; Fri, 13 Oct 2023 00:51:49 -0700 (PDT) Received: from localhost.localdomain (adsl-170.109.242.226.tellas.gr. [109.242.226.170]) by smtp.gmail.com with ESMTPSA id m8-20020adfa3c8000000b0032d7fde2d3csm7990663wrb.79.2023.10.13.00.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697183508; x=1697788308; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a7CRH59E7WDah93GOZUBpOMCM1LCjMQKDPJEI6Vj50o=; b=VVxEGwF5mDA5k2U0aJH9SnO/qFe3X3eCO8Q3Oj+mpSbm9BXi3thhOd8qRQGODIduZ0 dp1MT7RPjnNO8lPD6IwQkoxS7gEYc4lntEUs7/NEq/sxShCCmKnXwBqoMEIWeuVSfHv8 t0g6EgFtsEXeFGviyhpVmARLxxtxIwAPNLmf4XbU/CG9hu/KWgEW8ajHCLxvtw7olJsI Bal+PxQzcMxhAjwjIYGTZZGCt3RIdp7suTeykplTZIhFwpB71AbBdIVfFkP0AlkZsxkF AmhZcgt2Q9w8vV/QrPxvdJ71b+4KRLIiU8KiOhgcQMA0Uy/RCSiWC6INQUQcrnIjY075 uang== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697183508; x=1697788308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a7CRH59E7WDah93GOZUBpOMCM1LCjMQKDPJEI6Vj50o=; b=MNyj//KK+NclPpPmL+JpJ8rK1xc+MLF3jxuO+ivS4sOPHwkKRsFrP/yRdOOJzGTOCY IhHEcPZQXS5Et+38Ob02mBy7XW+O0rHefHG3/qiSRh49W4Q73a6dDuQWUtXIYlOOJ9+x c5kkl1WJqOfQxmCRpfZ3yyXN25Lg+zmyD0sL0TF86oH67TtY+IipjYiKt5hH/J4Ao9HG 283/4iED2PhSpuTSigzsbuUksCqOH3OePnsCz5RtrwxLMzLom5H0P5RatjWyajtFLLv1 sn7r2gamdL0SQTdpBWKFuAbvEg/Nvq6OMAqXzVZe3FGML2zM39W9WWYvpDO1bUnTFZmG g01g== X-Gm-Message-State: AOJu0YzhK5Ugo+qNhd7C23gEu/7jWVDLMt8phGcyHeRHvFBWSRCqVt5w FG54TRw3VVC1Ezbf36usAHUYO+5fRbmaxk7ZD2Q= X-Google-Smtp-Source: AGHT+IGWLDtFLRUfLHUUS+sLXT+wbczzg60UBYN297xc8aFmE3k9Qsked2RRE0ELbGgbJ9VCBT7nFg== X-Received: by 2002:adf:e19d:0:b0:32c:ea14:89e5 with SMTP id az29-20020adfe19d000000b0032cea1489e5mr10753805wrb.39.1697183508324; Fri, 13 Oct 2023 00:51:48 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org Cc: Emmanouil Pitsidianakis , Laurent Vivier , Gerd Hoffmann Subject: [RFC PATCH 50/78] hw/audio: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:48:08 +0300 Message-Id: <5fd3f2429559990851dba1e57dea59a2d83c0b18.1697183082.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697185404698100001 Content-Type: text/plain; charset="utf-8" In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- hw/audio/asc.c | 2 +- hw/audio/cs4231a.c | 2 +- hw/audio/gusemu_hal.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/audio/asc.c b/hw/audio/asc.c index 0f36b4ce9b..336da09509 100644 --- a/hw/audio/asc.c +++ b/hw/audio/asc.c @@ -154,126 +154,126 @@ static uint8_t asc_fifo_get(ASCFIFOState *fs) static int generate_fifo(ASCState *s, int maxsamples) { int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint8_t *buf =3D s->mixbuf; int i, wcount =3D 0; =20 while (wcount < maxsamples) { uint8_t val; int16_t d, f0, f1; int32_t t; int shift, filter; bool hasdata =3D false; =20 for (i =3D 0; i < 2; i++) { ASCFIFOState *fs =3D &s->fifos[i]; =20 switch (fs->extregs[ASC_EXTREGS_FIFOCTRL] & 0x83) { case 0x82: /* * CD-XA BRR mode: decompress 15 bytes into 28 16-bit * samples */ if (!fs->cnt) { val =3D 0x80; break; } =20 if (fs->xa_cnt =3D=3D -1) { /* Start of packet, get flags */ fs->xa_flags =3D asc_fifo_get(fs); fs->xa_cnt =3D 0; } =20 shift =3D fs->xa_flags & 0xf; filter =3D fs->xa_flags >> 4; f0 =3D (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT + (filter << 1) + 1]; f1 =3D (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT + (filter << 1)]; =20 if ((fs->xa_cnt & 1) =3D=3D 0) { if (!fs->cnt) { val =3D 0x80; break; } =20 fs->xa_val =3D asc_fifo_get(fs); d =3D (fs->xa_val & 0xf) << 12; } else { d =3D (fs->xa_val & 0xf0) << 8; } t =3D (d >> shift) + (((fs->xa_last[0] * f0) + (fs->xa_last[1] * f1) + 32) >> 6); if (t < -32768) { t =3D -32768; } else if (t > 32767) { t =3D 32767; } =20 /* * CD-XA BRR generates 16-bit signed output, so convert to * 8-bit before writing to buffer. Does real hardware do t= he * same? */ val =3D (uint8_t)(t / 256) ^ 0x80; hasdata =3D true; fs->xa_cnt++; =20 fs->xa_last[1] =3D fs->xa_last[0]; fs->xa_last[0] =3D (int16_t)t; =20 if (fs->xa_cnt =3D=3D 28) { /* End of packet */ fs->xa_cnt =3D -1; } break; =20 default: - /* fallthrough */ + fallthrough; case 0x80: /* Raw mode */ if (fs->cnt) { val =3D asc_fifo_get(fs); hasdata =3D true; } else { val =3D 0x80; } break; } =20 buf[wcount * 2 + i] =3D val; } =20 if (!hasdata) { break; } =20 wcount++; } =20 /* * MacOS (un)helpfully leaves the FIFO engine running even when it has * finished writing out samples, but still expects the FIFO empty * interrupts to be generated for each FIFO cycle (without these inter= rupts * MacOS will freeze) */ if (s->fifos[0].cnt =3D=3D 0 && s->fifos[1].cnt =3D=3D 0) { if (!s->fifo_empty_ns) { /* FIFO has completed first empty cycle */ s->fifo_empty_ns =3D now; } else if (now > (s->fifo_empty_ns + ASC_FIFO_CYCLE_TIME)) { /* FIFO has completed entire cycle with no data */ s->fifos[0].int_status |=3D ASC_FIFO_STATUS_HALF_FULL | ASC_FIFO_STATUS_FULL_EMPTY; s->fifos[1].int_status |=3D ASC_FIFO_STATUS_HALF_FULL | ASC_FIFO_STATUS_FULL_EMPTY; s->fifo_empty_ns =3D now; asc_raise_irq(s); } } else { /* FIFO contains data, reset empty time */ s->fifo_empty_ns =3D 0; } =20 return wcount; } diff --git a/hw/audio/cs4231a.c b/hw/audio/cs4231a.c index 3aa105748d..3bf0116c68 100644 --- a/hw/audio/cs4231a.c +++ b/hw/audio/cs4231a.c @@ -272,90 +272,90 @@ static void cs_audio_callback (void *opaque, int free) static void cs_reset_voices (CSState *s, uint32_t val) { int xtal; struct audsettings as; IsaDmaClass *k =3D ISADMA_GET_CLASS(s->isa_dma); =20 #ifdef DEBUG_XLAW if (val =3D=3D 0 || val =3D=3D 32) val =3D (1 << 4) | (1 << 5); #endif =20 xtal =3D val & 1; as.freq =3D freqs[xtal][(val >> 1) & 7]; =20 if (as.freq =3D=3D -1) { lerr ("unsupported frequency (val=3D%#x)\n", val); goto error; } =20 as.nchannels =3D (val & (1 << 4)) ? 2 : 1; as.endianness =3D 0; s->tab =3D NULL; =20 switch ((val >> 5) & ((s->dregs[MODE_And_ID] & MODE2) ? 7 : 3)) { case 0: as.fmt =3D AUDIO_FORMAT_U8; s->shift =3D as.nchannels =3D=3D 2; break; =20 case 1: s->tab =3D MuLawDecompressTable; goto x_law; case 3: s->tab =3D ALawDecompressTable; x_law: as.fmt =3D AUDIO_FORMAT_S16; as.endianness =3D AUDIO_HOST_ENDIANNESS; s->shift =3D as.nchannels =3D=3D 2; break; =20 case 6: as.endianness =3D 1; - /* fall through */ + fallthrough; case 2: as.fmt =3D AUDIO_FORMAT_S16; s->shift =3D as.nchannels; break; =20 case 7: case 4: lerr ("attempt to use reserved format value (%#x)\n", val); goto error; =20 case 5: lerr ("ADPCM 4 bit IMA compatible format is not supported\n"); goto error; } =20 s->voice =3D AUD_open_out ( &s->card, s->voice, "cs4231a", s, cs_audio_callback, &as ); =20 if (s->dregs[Interface_Configuration] & PEN) { if (!s->dma_running) { k->hold_DREQ(s->isa_dma, s->dma); AUD_set_active_out (s->voice, 1); s->transferred =3D 0; } s->dma_running =3D 1; } else { if (s->dma_running) { k->release_DREQ(s->isa_dma, s->dma); AUD_set_active_out (s->voice, 0); } s->dma_running =3D 0; } return; =20 error: if (s->dma_running) { k->release_DREQ(s->isa_dma, s->dma); AUD_set_active_out (s->voice, 0); } } diff --git a/hw/audio/gusemu_hal.c b/hw/audio/gusemu_hal.c index f159978b49..76dd906ea1 100644 --- a/hw/audio/gusemu_hal.c +++ b/hw/audio/gusemu_hal.c @@ -190,311 +190,311 @@ unsigned int gus_read(GUSEmuState * state, int port= , int size) void gus_write(GUSEmuState * state, int port, int size, unsigned int data) { uint8_t *gusptr; gusptr =3D state->gusdatapos; GUSregd(portaccesses)++; =20 switch (port & 0xff0f) { case 0x200: /* MixerCtrlReg */ GUSregb(MixerCtrlReg2x0) =3D (uint8_t) data; break; case 0x206: /* IRQstatReg / SB2x6IRQ */ if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6I= RQ bit */ { GUSregb(TimerStatus2x8) |=3D 0x08; GUSregb(IRQStatReg2x6) =3D 0x10; GUS_irqrequest(state, state->gusirq, 1); } break; case 0x308: /* AdLib 388h */ case 0x208: /* AdLibCommandReg */ GUSregb(AdLibCommand2xA) =3D (uint8_t) data; break; case 0x309: /* AdLib 389h */ case 0x209: /* AdLibDataReg */ if ((GUSregb(AdLibCommand2xA) =3D=3D 0x04) && (!(GUSregb(GUS45Time= rCtrl) & 1))) /* GUS auto timer mode enabled? */ { if (data & 0x80) GUSregb(TimerStatus2x8) &=3D 0x1f; /* AdLib IRQ reset? -> = clear maskable adl. timer int regs */ else GUSregb(TimerDataReg2x9) =3D (uint8_t) data; } else { GUSregb(AdLibData2x9) =3D (uint8_t) data; if (GUSregb(GUS45TimerCtrl) & 0x02) { GUSregb(TimerStatus2x8) |=3D 0x01; GUSregb(IRQStatReg2x6) =3D 0x10; GUS_irqrequest(state, state->gusirq, 1); } } break; case 0x20A: GUSregb(AdLibStatus2x8) =3D (uint8_t) data; break; /* AdLibStatus2x8 */ case 0x20B: /* GUS hidden registers */ switch (GUSregb(RegCtrl_2xF) & 0x7) { case 0: if (GUSregb(MixerCtrlReg2x0) & 0x40) GUSregb(IRQ_2xB) =3D (uint8_t) data; /* control register s= elect bit */ else GUSregb(DMA_2xB) =3D (uint8_t) data; break; /* case 1-4: general purpose emulation regs */ case 5: /* clear stat reg 2xF */ GUSregb(StatRead_2xF) =3D 0; /* ToDo: is this identical with G= US classic? */ if (!GUSregb(IRQStatReg2x6)) GUS_irqclear(state, state->gusirq); break; case 6: /* Jumper reg (Joystick= /MIDI enable) */ GUSregb(Jumper_2xB) =3D (uint8_t) data; break; default:; } break; case 0x20C: /* SB2xCd */ if (GUSregb(GUS45TimerCtrl) & 0x20) { GUSregb(TimerStatus2x8) |=3D 0x10; /* SB IRQ enabled? -> set 2= xCIRQ bit */ GUSregb(IRQStatReg2x6) =3D 0x10; GUS_irqrequest(state, state->gusirq, 1); } - /* fall through */ + fallthrough; case 0x20D: /* SB2xCd no IRQ */ GUSregb(SB2xCd) =3D (uint8_t) data; break; case 0x20E: /* SB2xE */ GUSregb(SB2xE) =3D (uint8_t) data; break; case 0x20F: GUSregb(RegCtrl_2xF) =3D (uint8_t) data; break; /* CtrlReg2xF */ case 0x302: /* VoiceSelReg */ GUSregb(VoiceSelReg3x2) =3D (uint8_t) data; break; case 0x303: /* FunkSelReg */ GUSregb(FunkSelReg3x3) =3D (uint8_t) data; if ((uint8_t) data =3D=3D 0x8f) /* set irqstatreg, get voicereg an= d clear IRQ */ { int voice; if (GUSregd(voicewavetableirq)) /* WavetableIRQ */ { for (voice =3D 0; voice < 31; voice++) { if (GUSregd(voicewavetableirq) & (1 << voice)) { GUSregd(voicewavetableirq) ^=3D (1 << voice); /* c= lear IRQ bit */ GUSregb(voice << 5) &=3D 0x7f; /* clear voice reg = irq bit */ if (!GUSregd(voicewavetableirq)) GUSregb(IRQStatReg2x6) &=3D 0xdf; if (!GUSregb(IRQStatReg2x6)) GUS_irqclear(state, state->gusirq); GUSregb(SynVoiceIRQ8f) =3D voice | 0x60; /* (bit= =3D=3D0 =3D> IRQ wartend) */ return; } } } else if (GUSregd(voicevolrampirq)) /* VolRamp IRQ */ { for (voice =3D 0; voice < 31; voice++) { if (GUSregd(voicevolrampirq) & (1 << voice)) { GUSregd(voicevolrampirq) ^=3D (1 << voice); /* cle= ar IRQ bit */ GUSregb((voice << 5) + VSRVolRampControl) &=3D 0x7= f; /* clear voice volume reg irq bit */ if (!GUSregd(voicevolrampirq)) GUSregb(IRQStatReg2x6) &=3D 0xbf; if (!GUSregb(IRQStatReg2x6)) GUS_irqclear(state, state->gusirq); GUSregb(SynVoiceIRQ8f) =3D voice | 0x80; /* (bit= =3D=3D0 =3D> IRQ wartend) */ return; } } } GUSregb(SynVoiceIRQ8f) =3D 0xe8; /* kein IRQ wartet */ } break; case 0x304: case 0x305: { uint16_t writedata =3D (uint16_t) data; uint16_t readmask =3D 0x0000; if (size =3D=3D 1) { readmask =3D 0xff00; writedata &=3D 0xff; if ((port & 0xff0f) =3D=3D 0x305) { writedata =3D (uint16_t) (writedata << 8); readmask =3D 0x00ff; } } switch (GUSregb(FunkSelReg3x3)) { /* voice specific functions */ case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: { int offset; if (!(GUSregb(GUS4cReset) & 0x01)) break; /* reset flag active? */ offset =3D 2 * (GUSregb(FunkSelReg3x3) & 0x0f); offset +=3D (GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = =3D Voice*32 + Function*2 */ GUSregw(offset) =3D (uint16_t) ((GUSregw(offset) & rea= dmask) | writedata); } break; /* voice unspecific functions */ case 0x0e: /* NumVoices */ GUSregb(NumVoices) =3D (uint8_t) data; break; /* case 0x0f: */ /* read only */ /* common functions */ case 0x41: /* DramDMAContrReg */ GUSregb(GUS41DMACtrl) =3D (uint8_t) data; if (data & 0x01) GUS_dmarequest(state); break; case 0x42: /* DramDMAmemPosReg */ GUSregw(GUS42DMAStart) =3D (GUSregw(GUS42DMAStart) & readm= ask) | writedata; GUSregb(GUS50DMAHigh) &=3D 0xf; /* compatibility stuff... = */ break; case 0x43: /* DRAMaddrLo */ GUSregd(GUSDRAMPOS24bit) =3D (GUSregd(GUSDRAMPOS24bit) & (readmask | 0xff0000)) | w= ritedata; break; case 0x44: /* DRAMaddrHi */ GUSregd(GUSDRAMPOS24bit) =3D (GUSregd(GUSDRAMPOS24bit) & 0xffff) | ((data & 0x0f) <= < 16); break; case 0x45: /* TCtrlReg */ GUSregb(GUS45TimerCtrl) =3D (uint8_t) data; if (!(data & 0x20)) GUSregb(TimerStatus2x8) &=3D 0xe7; /* sb IRQ dis? -= > clear 2x8/2xC sb IRQ flags */ if (!(data & 0x02)) GUSregb(TimerStatus2x8) &=3D 0xfe; /* adlib data IR= Q dis? -> clear 2x8 adlib IRQ flag */ if (!(GUSregb(TimerStatus2x8) & 0x19)) GUSregb(IRQStatReg2x6) &=3D 0xef; /* 0xe6; $$clear= IRQ if both IRQ bits are inactive or cleared */ /* catch up delayed timer IRQs: */ if ((GUSregw(TimerIRQs) > 1) && (GUSregb(TimerDataReg2x9) = & 3)) { if (GUSregb(TimerDataReg2x9) & 1) /* start timer 1 (= 80us decrement rate) */ { if (!(GUSregb(TimerDataReg2x9) & 0x40)) GUSregb(TimerStatus2x8) |=3D 0xc0; /* maska= ble bits */ if (data & 4) /* timer1 irq enable */ { GUSregb(TimerStatus2x8) |=3D 4; /* nonma= skable bit */ GUSregb(IRQStatReg2x6) |=3D 4; /* timer= 1 irq pending */ } } if (GUSregb(TimerDataReg2x9) & 2) /* start timer 2 (= 320us decrement rate) */ { if (!(GUSregb(TimerDataReg2x9) & 0x20)) GUSregb(TimerStatus2x8) |=3D 0xa0; /* maska= ble bits */ if (data & 8) /* timer2 irq enable */ { GUSregb(TimerStatus2x8) |=3D 2; /* nonma= skable bit */ GUSregb(IRQStatReg2x6) |=3D 8; /* timer= 2 irq pending */ } } GUSregw(TimerIRQs)--; if (GUSregw(BusyTimerIRQs) > 1) GUSregw(BusyTimerIRQs)--; else GUSregw(BusyTimerIRQs) =3D GUS_irqrequest(state, state->gusirq, GUSregw(T= imerIRQs)); } else GUSregw(TimerIRQs) =3D 0; =20 if (!(data & 0x04)) { GUSregb(TimerStatus2x8) &=3D 0xfb; /* clear non-maskab= le timer1 bit */ GUSregb(IRQStatReg2x6) &=3D 0xfb; } if (!(data & 0x08)) { GUSregb(TimerStatus2x8) &=3D 0xfd; /* clear non-maskab= le timer2 bit */ GUSregb(IRQStatReg2x6) &=3D 0xf7; } if (!GUSregb(IRQStatReg2x6)) GUS_irqclear(state, state->gusirq); break; case 0x46: /* Counter1 */ GUSregb(GUS46Counter1) =3D (uint8_t) data; break; case 0x47: /* Counter2 */ GUSregb(GUS47Counter2) =3D (uint8_t) data; break; /* case 0x48: */ /* sampling freq reg not emulated (same= as interwave) */ case 0x49: /* SampCtrlReg */ GUSregb(GUS49SampCtrl) =3D (uint8_t) data; break; /* case 0x4b: */ /* joystick trim not emulated */ case 0x4c: /* GUSreset */ GUSregb(GUS4cReset) =3D (uint8_t) data; if (!(GUSregb(GUS4cReset) & 1)) /* reset... */ { GUSregd(voicewavetableirq) =3D 0; GUSregd(voicevolrampirq) =3D 0; GUSregw(TimerIRQs) =3D 0; GUSregw(BusyTimerIRQs) =3D 0; GUSregb(NumVoices) =3D 0xcd; GUSregb(IRQStatReg2x6) =3D 0; GUSregb(TimerStatus2x8) =3D 0; GUSregb(AdLibData2x9) =3D 0; GUSregb(TimerDataReg2x9) =3D 0; GUSregb(GUS41DMACtrl) =3D 0; GUSregb(GUS45TimerCtrl) =3D 0; GUSregb(GUS49SampCtrl) =3D 0; GUSregb(GUS4cReset) &=3D 0xf9; /* clear IRQ and DAC en= able bits */ GUS_irqclear(state, state->gusirq); } /* IRQ enable bit checked elsewhere */ /* EnableDAC bit may be used by external callers */ break; } } break; case 0x307: /* DRAMaccess */ { uint8_t *adr; adr =3D state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff= ); *adr =3D (uint8_t) data; } break; } } =20 /* Attention when breaking up a single DMA transfer to multiple ones: * it may lead to multiple terminal count interrupts and broken transfers: * * 1. Whenever you transfer a piece of data, the gusemu callback is invoked * 2. The callback may generate a TC irq (if the register was set up to do= so) * 3. The irq may result in the program using the GUS to reprogram the GUS * * Some programs also decide to upload by just checking if TC occurs * (via interrupt or a cleared GUS dma flag) * and then start the next transfer, without checking DMA state * * Thus: Always make sure to set the TC flag correctly! * * Note that the genuine GUS had a granularity of 16 bytes/words for low/h= igh DMA * while later cards had atomic granularity provided by an additional GUS5= 0DMAHigh register * GUSemu also uses this register to support byte-granular transfers for b= etter compatibility * with emulators other than GUSemu32 */ --=20 2.39.2