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X-Received-From: 216.71.154.42 Subject: [Qemu-devel] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , "palmer@sifive.com" , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) Content-Type: text/plain; charset="utf-8" From: Michael Clark Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Michael Clark Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6d3fbc3401..b17f169681 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -525,7 +525,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); } - /* TODO yield load reservation */ + + /* NOTE: it is not necessary to yield load reservations here. It is on= ly + * necessary for an SC from "another hart" to cause a load reservation + * to be yielded. Refer to the memory consistency model section of the + * RISC-V ISA Specification. + */ + #endif cs->exception_index =3D EXCP_NONE; /* mark handled to qemu */ } --=20 2.21.0