From nobody Tue Nov 18 09:18:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1609032268; cv=none; d=zohomail.com; s=zohoarc; b=NNHHCMMcEswjsDdJxRMcuVKi6BlxU9VAw1g7xdIozoRZLQPFl0nre2zXXqL3cg5kgjNTXC6QO5dhDoFSO9RSQVdVkKyu0PLuFP/7VnXX+JleSAYHTrUhRjb56VzJjDe39P7Ek/Ap/gfSjIpp/VDwyJMeabaKYADGSGd6sk6fdU8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609032268; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=62Tlavq6Fzn7wqNipKC4UQlkSOoaV5JehLoQ5hKL82A=; b=B6Gpv3U1hpH9b4xmx8jg8kG7zGJK8tEc4qt4ymWu7b0KSlE5lIlG8RKAYv6Cl0ZSziTkgVQBYITAKfprK1zqmc7ONe9YbfxlFGajvkMe+bXh0uq5g0dxs2PPZd1Nq7K/KSxLZW/At6oR9IaidCrUEa9CwUl0BIpujn0BaHsSnjc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1609032268613244.3221331849836; Sat, 26 Dec 2020 17:24:28 -0800 (PST) Received: from localhost ([::1]:37296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ktKnL-0001np-Te for importer@patchew.org; Sat, 26 Dec 2020 20:24:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33302) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ktKkY-0008TW-CP for qemu-devel@nongnu.org; Sat, 26 Dec 2020 20:21:35 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:61531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ktKkS-0001Dq-RE for qemu-devel@nongnu.org; Sat, 26 Dec 2020 20:21:34 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 9F7667470F1; Sun, 27 Dec 2020 02:21:18 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id EE9A97470DF; Sun, 27 Dec 2020 02:21:17 +0100 (CET) Message-Id: <599e3174ab2cbe105d17733ae25c1a7f22030dcb.1609031406.git.balaton@eik.bme.hu> In-Reply-To: References: Subject: [PATCH 11/12] vt82c686: Rename some functions to better show where they belong Date: Sun, 27 Dec 2020 02:10:06 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: BALATON Zoltan From: BALATON Zoltan via Content-Type: text/plain; charset="utf-8" This groups identifiers related to the ISA bridge part and superio part also in their naming. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/vt82c686.c | 48 ++++++++++++++++++--------------------- hw/mips/fuloong2e.c | 2 +- include/hw/isa/vt82c686.h | 2 +- 3 files changed, 24 insertions(+), 28 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 6dff2bc67d..698627d1b5 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -36,10 +36,10 @@ struct VT82C686BState { SuperIOConfig superio_conf; }; =20 -OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BState, VT82C686B) +OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BState, VT82C686B_ISA) =20 -static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, - unsigned size) +static void vt82c686b_superio_writeb(void *opaque, hwaddr addr, uint64_t d= ata, + unsigned size) { SuperIOConfig *superio_conf =3D opaque; =20 @@ -72,7 +72,8 @@ static void superio_ioport_writeb(void *opaque, hwaddr ad= dr, uint64_t data, } } =20 -static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned s= ize) +static uint64_t vt82c686b_superio_readb(void *opaque, hwaddr addr, + unsigned size) { SuperIOConfig *superio_conf =3D opaque; uint8_t val =3D superio_conf->config[superio_conf->index]; @@ -81,9 +82,9 @@ static uint64_t superio_ioport_readb(void *opaque, hwaddr= addr, unsigned size) return val; } =20 -static const MemoryRegionOps superio_ops =3D { - .read =3D superio_ioport_readb, - .write =3D superio_ioport_writeb, +static const MemoryRegionOps vt82c686b_superio_ops =3D { + .read =3D vt82c686b_superio_readb, + .write =3D vt82c686b_superio_writeb, .endianness =3D DEVICE_NATIVE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -93,7 +94,7 @@ static const MemoryRegionOps superio_ops =3D { =20 static void vt82c686b_isa_reset(DeviceState *dev) { - VT82C686BState *vt82c =3D VT82C686B(dev); + VT82C686BState *vt82c =3D VT82C686B_ISA(dev); uint8_t *pci_conf =3D vt82c->dev.config; =20 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); @@ -118,11 +119,10 @@ static void vt82c686b_isa_reset(DeviceState *dev) vt82c->superio_conf.config[0xe8] =3D 0xbe; } =20 -/* write config pci function0 registers. PCI-ISA bridge */ -static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, +static void vt82c686b_isa_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) { - VT82C686BState *vt686 =3D VT82C686B(d); + VT82C686BState *vt686 =3D VT82C686B_ISA(d); =20 trace_via_isa_write(addr, val, len); pci_default_write_config(d, addr, val, len); @@ -284,10 +284,9 @@ static const VMStateDescription vmstate_via =3D { } }; =20 -/* init the PCI-to-ISA bridge */ -static void vt82c686b_realize(PCIDevice *d, Error **errp) +static void vt82c686b_isa_realize(PCIDevice *d, Error **errp) { - VT82C686BState *vt82c =3D VT82C686B(d); + VT82C686BState *vt82c =3D VT82C686B_ISA(d); uint8_t *pci_conf; ISABus *isa_bus; uint8_t *wmask; @@ -309,7 +308,7 @@ static void vt82c686b_realize(PCIDevice *d, Error **err= p) } } =20 - memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, + memory_region_init_io(&vt82c->superio, OBJECT(d), &vt82c686b_superio_o= ps, &vt82c->superio_conf, "superio", 2); memory_region_set_enabled(&vt82c->superio, false); /* @@ -320,13 +319,13 @@ static void vt82c686b_realize(PCIDevice *d, Error **e= rrp) &vt82c->superio); } =20 -static void via_class_init(ObjectClass *klass, void *data) +static void via_isa_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->realize =3D vt82c686b_realize; - k->config_write =3D vt82c686b_write_config; + k->realize =3D vt82c686b_isa_realize; + k->config_write =3D vt82c686b_isa_write_config; k->vendor_id =3D PCI_VENDOR_ID_VIA; k->device_id =3D PCI_DEVICE_ID_VIA_ISA_BRIDGE; k->class_id =3D PCI_CLASS_BRIDGE_ISA; @@ -334,18 +333,15 @@ static void via_class_init(ObjectClass *klass, void *= data) dc->reset =3D vt82c686b_isa_reset; dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_via; - /* - * Reason: part of VIA VT82C686 southbridge, needs to be wired up, - * e.g. by mips_fuloong2e_init() - */ + /* Reason: Part of VIA southbridge, needs to be wired up by board code= */ dc->user_creatable =3D false; } =20 -static const TypeInfo via_info =3D { - .name =3D TYPE_VT82C686B, +static const TypeInfo via_isa_info =3D { + .name =3D TYPE_VT82C686B_ISA, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(VT82C686BState), - .class_init =3D via_class_init, + .class_init =3D via_isa_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, @@ -374,7 +370,7 @@ static void vt82c686b_register_types(void) { type_register_static(&via_pm_info); type_register_static(&via_superio_info); - type_register_static(&via_info); + type_register_static(&via_isa_info); } =20 type_init(vt82c686b_register_types) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index d275038830..a2b69a3a7a 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -241,7 +241,7 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus,= int slot, qemu_irq intc, PCIDevice *dev; =20 dev =3D pci_create_simple_multifunction(pci_bus, PCI_DEVFN(slot, 0), t= rue, - TYPE_VT82C686B); + TYPE_VT82C686B_ISA); isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0")); assert(isa_bus); *p_isa_bus =3D isa_bus; diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index 080ee8fc59..5b0a1ffe72 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -1,7 +1,7 @@ #ifndef HW_VT82C686_H #define HW_VT82C686_H =20 -#define TYPE_VT82C686B "vt82c686b" +#define TYPE_VT82C686B_ISA "vt82c686b-isa" #define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" #define TYPE_VT82C686B_PM "vt82c686b-pm" #define TYPE_VIA_AC97 "via-ac97" --=20 2.21.3