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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 193 ++++++++++++++++++++++++++++++++++---- 2 files changed, 175 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa04e5cca7..a8534fdf2b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -104,6 +104,7 @@ struct CPURISCVState { target_ulong frm; =20 target_ulong badaddr; + target_ulong guest_phys_fault_addr; =20 target_ulong priv_ver; target_ulong misa; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index cd2d9341b9..5f96631637 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -285,11 +285,12 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ul= ong newpriv) * @mmu_idx: Indicates current privilege level * @first_stage: Are we in first stage translation? * Second stage is used for hypervisor guest translation + * @two_stage: Are we going to perform two stage translation */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *prot, target_ulong addr, int access_type, int mmu_idx, - bool first_stage) + bool first_stage, bool two_stage) { /* NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler @@ -297,13 +298,40 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; int mode =3D mmu_idx; + bool use_background =3D false; =20 + /* + * Check if we should use the background registers for the two + * stage translation. We don't need to check if we actually need + * two stage translation as that happened before this function + * was called. Background registers will be used if the guest has + * forced a two stage translation to be on (in HS or M mode). + */ if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); + + if (riscv_has_ext(env, RVH) && + get_field(env->mstatus, MSTATUS_MPV)) { + use_background =3D true; + } + } + } + + if (mode =3D=3D PRV_S && access_type !=3D MMU_INST_FETCH && + riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + if (get_field(env->hstatus, HSTATUS_SPRV)) { + mode =3D get_field(env->mstatus, SSTATUS_SPP); + use_background =3D true; } } =20 + if (first_stage =3D=3D false) { + /* We are in stage 2 translation, this is similar to stage 1. */ + /* Stage 2 is always taken as U-mode */ + mode =3D PRV_U; + } + if (mode =3D=3D PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { *physical =3D addr; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -313,13 +341,30 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, *prot =3D 0; =20 hwaddr base; - int levels, ptidxbits, ptesize, vm, sum; - int mxr =3D get_field(env->mstatus, MSTATUS_MXR); + int levels, ptidxbits, ptesize, vm, sum, mxr, widened; + + if (first_stage =3D=3D true) { + mxr =3D get_field(env->mstatus, MSTATUS_MXR); + } else { + mxr =3D get_field(env->vsstatus, MSTATUS_MXR); + } =20 if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + if (first_stage =3D=3D true) { + if (use_background) { + base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIF= T; + vm =3D get_field(env->vsatp, SATP_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP_MODE); + } + widened =3D 0; + } else { + base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, HGATP_MODE); + widened =3D 2; + } sum =3D get_field(env->mstatus, MSTATUS_SUM); - vm =3D get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; @@ -337,6 +382,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, g_assert_not_reached(); } } else { + widened =3D 0; base =3D (hwaddr)(env->sptbr) << PGSHIFT; sum =3D !get_field(env->mstatus, MSTATUS_PUM); vm =3D get_field(env->mstatus, MSTATUS_VM); @@ -357,9 +403,16 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, } =20 CPUState *cs =3D env_cpu(env); - int va_bits =3D PGSHIFT + levels * ptidxbits; - target_ulong mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; - target_ulong masked_msbs =3D (addr >> (va_bits - 1)) & mask; + int va_bits =3D PGSHIFT + levels * ptidxbits + widened; + target_ulong mask, masked_msbs; + + if (TARGET_LONG_BITS > (va_bits - 1)) { + mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; + } else { + mask =3D 0; + } + masked_msbs =3D (addr >> (va_bits - 1)) & mask; + if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { return TRANSLATE_FAIL; } @@ -371,11 +424,29 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, restart: #endif for (i =3D 0; i < levels; i++, ptshift -=3D ptidxbits) { - target_ulong idx =3D (addr >> (PGSHIFT + ptshift)) & + target_ulong idx; + if (i =3D=3D 0) { + idx =3D (addr >> (PGSHIFT + ptshift)) & + ((1 << (ptidxbits + widened)) - 1); + } else { + idx =3D (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1); + } =20 /* check that physical address of PTE is legal */ - hwaddr pte_addr =3D base + idx * ptesize; + hwaddr pte_addr; + + if (two_stage && first_stage) { + hwaddr vbase; + + /* Do the second stage translation on the base PTE address. */ + get_physical_address(env, &vbase, prot, base, access_type, + mmu_idx, false, true); + + pte_addr =3D vbase + idx * ptesize; + } else { + pte_addr =3D base + idx * ptesize; + } =20 if (riscv_feature(env, RISCV_FEATURE_PMP) && !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), @@ -472,7 +543,12 @@ restart: /* for superpage mappings, make a fake leaf PTE for the TLB's benefit. */ target_ulong vpn =3D addr >> PGSHIFT; - *physical =3D (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; + if (i =3D=3D 0) { + *physical =3D (ppn | (vpn & ((1L << (ptshift + widened)) -= 1))) << + PGSHIFT; + } else { + *physical =3D (ppn | (vpn & ((1L << ptshift) - 1))) << PGS= HIFT; + } =20 /* set permissions on the TLB entry */ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { @@ -529,14 +605,23 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; hwaddr phys_addr; int prot; int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_id= x, - true)) { + if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, + true, riscv_cpu_virt_enabled(env))) { return -1; } + + if (riscv_cpu_virt_enabled(env)) { + if (get_physical_address(env, &phys_addr, &prot, phys_addr, + 0, mmu_idx, false, true)) { + return -1; + } + } + return phys_addr; } =20 @@ -590,17 +675,37 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; #ifndef CONFIG_USER_ONLY + vaddr im_address; hwaddr pa =3D 0; int prot; bool pmp_violation =3D false; + bool m_mode_two_stage =3D false; + bool hs_mode_two_stage =3D false; + bool first_stage_error =3D true; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; =20 + env->guest_phys_fault_addr =3D 0; + qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx, - true); + /* + * Determine if we are in M mode and MPRV is set or in HS mode and SPR= V is + * set and we want to access a virtulisation address. + */ + if (riscv_has_ext(env, RVH)) { + m_mode_two_stage =3D env->priv =3D=3D PRV_M && + access_type !=3D MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MPV); + + hs_mode_two_stage =3D env->priv =3D=3D PRV_S && + !riscv_cpu_virt_enabled(env) && + access_type !=3D MMU_INST_FETCH && + get_field(env->hstatus, HSTATUS_SPRV) && + get_field(env->hstatus, HSTATUS_SPV); + } =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { @@ -608,9 +713,55 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } } =20 - qemu_log_mask(CPU_LOG_MMU, - "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_F= MT_plx - " prot %d\n", __func__, address, ret, pa, prot); + if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_sta= ge) { + /* Two stage lookup */ + ret =3D get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, true); + + qemu_log_mask(CPU_LOG_MMU, + "%s 1st-stage address=3D%" VADDR_PRIx " ret %d physi= cal " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + + if (ret !=3D TRANSLATE_FAIL) { + /* Second stage lookup */ + im_address =3D pa; + + ret =3D get_physical_address(env, &pa, &prot, im_address, + access_type, mmu_idx, false, true); + + qemu_log_mask(CPU_LOG_MMU, + "%s 2nd-stage address=3D%" VADDR_PRIx " ret %d physica= l " + TARGET_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + (ret =3D=3D TRANSLATE_SUCCESS) && + !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)= ) { + ret =3D TRANSLATE_PMP_FAIL; + } + + if (ret !=3D TRANSLATE_SUCCESS) { + /* + * Guest physical address translation failed, this is a HS + * level exception + */ + first_stage_error =3D false; + env->guest_phys_fault_addr =3D (im_address | + (address & + (TARGET_PAGE_SIZE - 1))) >>= 2; + } + } + } else { + /* Single stage lookup */ + ret =3D get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, false); + + qemu_log_mask(CPU_LOG_MMU, + "%s address=3D%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + } =20 if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret =3D=3D TRANSLATE_SUCCESS) && @@ -620,6 +771,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (ret =3D=3D TRANSLATE_PMP_FAIL) { pmp_violation =3D true; } + if (ret =3D=3D TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); @@ -627,9 +779,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation, true= ); + raise_mmu_exception(env, address, access_type, pmp_violation, firs= t_stage_error); riscv_raise_exception(env, cs->exception_index, retaddr); } + + return true; + #else switch (access_type) { case MMU_INST_FETCH: --=20 2.25.0