From nobody Sun Feb 8 21:06:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663156827269794.7295353104021; Wed, 14 Sep 2022 05:00:27 -0700 (PDT) Received: from localhost ([::1]:58666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYR43-0007qL-Dw for importer@patchew.org; Wed, 14 Sep 2022 08:00:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYQet-00047r-DP; Wed, 14 Sep 2022 07:34:23 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:42848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYQer-0005YL-8E; Wed, 14 Sep 2022 07:34:23 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 9DBF7746397; Wed, 14 Sep 2022 13:34:19 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 678CA74633F; Wed, 14 Sep 2022 13:34:19 +0200 (CEST) Message-Id: <53f8420bf31535257075e2d53368aa6011c5443b.1663154398.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v4 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Wed, 14 Sep 2022 13:34:19 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663156829203100001 Content-Type: text/plain; charset="utf-8" Instead of checking if memory size is valid in board code move this check to ppc4xx_sdram_init() as this is a restriction imposed by the SDRAM controller. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/ppc405.h | 2 -- hw/ppc/ppc405_boards.c | 10 ---------- hw/ppc/ppc405_uc.c | 11 ++--------- hw/ppc/ppc440_bamboo.c | 10 +--------- hw/ppc/ppc4xx_devs.c | 14 ++++++-------- include/hw/ppc/ppc4xx.h | 2 +- 6 files changed, 10 insertions(+), 39 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index ca0972b88b..ad54dff542 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -167,9 +167,7 @@ struct Ppc405SoCState { DeviceState parent_obj; =20 /* Public */ - Ppc4xxSdramBank ram_banks[2]; MemoryRegion *dram_mr; - hwaddr ram_size; =20 PowerPCCPU cpu; PPCUIC uic; diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index bf02a71c6d..cdd4e0cb4c 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -271,22 +271,12 @@ static void boot_from_kernel(MachineState *machine, P= owerPCCPU *cpu) static void ppc405_init(MachineState *machine) { Ppc405MachineState *ppc405 =3D PPC405_MACHINE(machine); - MachineClass *mc =3D MACHINE_GET_CLASS(machine); const char *kernel_filename =3D machine->kernel_filename; MemoryRegion *sysmem =3D get_system_memory(); CPUPPCState *env; =20 - if (machine->ram_size !=3D mc->default_ram_size) { - char *sz =3D size_to_str(mc->default_ram_size); - error_report("Invalid RAM size, should be %s", sz); - g_free(sz); - exit(EXIT_FAILURE); - } - object_initialize_child(OBJECT(machine), "soc", &ppc405->soc, TYPE_PPC405_SOC); - object_property_set_uint(OBJECT(&ppc405->soc), "ram-size", - machine->ram_size, &error_fatal); object_property_set_link(OBJECT(&ppc405->soc), "dram", OBJECT(machine->ram), &error_abort); object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333, diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index bcbf35bc14..e1c7188e61 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1073,15 +1073,9 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT= )); =20 /* SDRAM controller */ - /* XXX 405EP has no ECC interrupt */ - s->ram_banks[0].base =3D 0; - s->ram_banks[0].size =3D s->ram_size; - memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s), - "ppc405.sdram0", s->dram_mr, - s->ram_banks[0].base, s->ram_banks[0].size); - + /* XXX 405EP has no ECC interrupt */ ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1, - s->ram_banks); + s->dram_mr); =20 /* External bus controller */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { @@ -1159,7 +1153,6 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) static Property ppc405_soc_properties[] =3D { DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 2bd5e41140..9b456f1819 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -50,10 +50,6 @@ =20 #define PPC440EP_SDRAM_NR_BANKS 4 =20 -static const ram_addr_t ppc440ep_sdram_bank_sizes[] =3D { - 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0 -}; - static hwaddr entry; =20 static int bamboo_load_device_tree(hwaddr addr, @@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine) unsigned int pci_irq_nrs[4] =3D { 28, 27, 26, 25 }; MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *isa =3D g_new(MemoryRegion, 1); - Ppc4xxSdramBank *ram_banks =3D g_new0(Ppc4xxSdramBank, - PPC440EP_SDRAM_NR_BANKS); PCIBus *pcibus; PowerPCCPU *cpu; CPUPPCState *env; @@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine) qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); =20 /* SDRAM controller */ - ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks, - ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0= . */ ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14), - PPC440EP_SDRAM_NR_BANKS, ram_banks); + PPC440EP_SDRAM_NR_BANKS, machine->ram); /* Enable SDRAM memory regions, this should be done by the firmware */ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) || ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) { diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 7bdcbd6fac..eb3aa97b16 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -41,7 +41,7 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; struct ppc4xx_sdram_t { uint32_t addr; - int nbanks; + int nbanks; /* Banks to use from the 4, e.g. when board has less slots= */ Ppc4xxSdramBank bank[4]; uint32_t besr0; uint32_t besr1; @@ -343,19 +343,17 @@ static void sdram_reset(void *opaque) } =20 void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, - Ppc4xxSdramBank *ram_banks) + MemoryRegion *ram) { ppc4xx_sdram_t *sdram; - int i; + const ram_addr_t valid_bank_sizes[] =3D { + 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * M= iB, 0 + }; =20 sdram =3D g_new0(ppc4xx_sdram_t, 1); sdram->irq =3D irq; sdram->nbanks =3D nbanks; - for (i =3D 0; i < nbanks; i++) { - sdram->bank[i].ram =3D ram_banks[i].ram; - sdram->bank[i].base =3D ram_banks[i].base; - sdram->bank[i].size =3D ram_banks[i].size; - } + ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes); qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, sdram, &dcr_read_sdram, &dcr_write_sdram); diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 5013b8bf3a..6007a8dd04 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -47,7 +47,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, const ram_addr_t sdram_bank_sizes[]); =20 void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, - Ppc4xxSdramBank *ram_banks); + MemoryRegion *ram); =20 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 --=20 2.30.4