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Sat, 07 Mar 2026 23:18:40 -0800 (PST) From: Chao Liu To: Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier Cc: tangtao1634@phytium.com.cn, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 02/28] target/riscv: keep Debug Mode active when a DM ROM is present Date: Sun, 8 Mar 2026 15:17:05 +0800 Message-ID: <50bb827520cc1fc9e913a6293e5fe30c355a5a69.1772936778.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1341; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772954428333154100 Content-Type: text/plain; charset="utf-8" Record whether a hart has a Debug Module ROM entry point and keep the CPU in Debug Mode while that ROM is active, instead of always returning to dpc on the next exec loop entry. This updates Debug Mode entry so dpc follows the architectural cause rules, switches ROM and Program Buffer execution to M-mode, and lets later DM patches hand control to the ROM park loop. Signed-off-by: Chao Liu --- target/riscv/cpu.h | 4 +++- target/riscv/cpu_helper.c | 27 ++++++++++++++++++++++++++- target/riscv/tcg/tcg-cpu.c | 10 ++++++++++ 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6fb255c7c3..0bc14f6953 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -481,9 +481,11 @@ struct CPUArchState { target_ulong dpc; target_ulong dscratch[2]; =20 - /* Pending Debug Module halt request from the board-level controller. = */ + /* DM halt request (set by external Debug Module GPIO) */ bool dm_halt_request; uint8_t dm_halt_cause; + bool dm_rom_present; + uint64_t dm_halt_addr; =20 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a0874f4e23..714dcb446e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -141,6 +141,24 @@ static bool riscv_sdext_enabled(CPURISCVState *env) { return riscv_cpu_cfg(env)->ext_sdext; } + +/* + * Debug Spec v1.0 Table 9: + * - ebreak: dpc =3D address of the ebreak instruction. + * - step/trigger/haltreq (and reset/group/other): dpc =3D next instruction + * to execute when Debug Mode was entered. + */ +static target_ulong riscv_debug_dpc_on_entry(CPURISCVState *env, + target_ulong trap_pc, + uint32_t cause) +{ + switch (cause & 0x7) { + case DCSR_CAUSE_EBREAK: + return trap_pc & get_xepc_mask(env); + default: + return env->pc & get_xepc_mask(env); + } +} #endif =20 void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc, @@ -152,7 +170,7 @@ void riscv_cpu_enter_debug_mode(CPURISCVState *env, tar= get_ulong pc, } =20 env->debug_mode =3D true; - env->dpc =3D pc & get_xepc_mask(env); + env->dpc =3D riscv_debug_dpc_on_entry(env, pc, cause); env->dcsr &=3D ~(DCSR_CAUSE_MASK | DCSR_PRV_MASK | DCSR_V); env->dcsr |=3D ((target_ulong)(cause & 0x7)) << DCSR_CAUSE_SHIFT; env->dcsr |=3D env->priv & DCSR_PRV_MASK; @@ -168,6 +186,13 @@ void riscv_cpu_enter_debug_mode(CPURISCVState *env, ta= rget_ulong pc, } env->elp =3D false; } + + /* + * Per RISC-V Debug Spec v1.0 Section 4.1: + * "All operations are executed with machine mode privilege." + * Switch to M-mode so ROM/progbuf fetches use physical addressing. + */ + riscv_cpu_set_mode(env, PRV_M, false); #endif } =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 53d862080c..4674ff3e3c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -280,6 +280,16 @@ static void riscv_cpu_exec_enter(CPUState *cs) if (!cpu->cfg.ext_sdext || !env->debug_mode) { return; } + + /* + * When a DM ROM is present, the CPU must stay in debug mode and + * execute ROM code. DRET will leave debug mode later. Without a DM + * ROM, leave debug mode immediately (legacy shortcut). + */ + if (env->dm_rom_present) { + return; + } + target_ulong pc =3D env->dpc; riscv_cpu_leave_debug_mode(env); env->pc =3D pc; --=20 2.53.0