From nobody Tue Nov 18 10:40:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1609586442; cv=none; d=zohomail.com; s=zohoarc; b=ew+42koIJsh3sTVdNl46QddFBefQaekAAn1+/ecgOqVaaVzC9U3DtxVpBrnmN+//RawDoAiffL6wlFSrwYOZX3025ClOLljvCaLtE/d1mzIRDcg7cYt/e9FNBYEwxyoP/k5dnLwTfumwSHa+V46Xb3POoSttYcsyLiY1Fm5nqfM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609586442; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=VKrycvbN3vhNaPdXUZ4JEvhlG5GjFpmfJlaaFhV8+do=; b=locg+x5j2kugS4CPIo9Cjuoiu0zrRwXazOSTXEPDykr+Kk5lLX2E2CdIsVOIsatWjSg1fNpWJn/jndj8Ql+8xyk+mXekeIYa5B9oLRfDtIDAi3beREln7AZTUjjGIw4v2xRoaLZRPr0Li9nZT/ss3XQkQ8esRbUeYhta98iN47g= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1609586442712989.5500013362273; Sat, 2 Jan 2021 03:20:42 -0800 (PST) Received: from localhost ([::1]:37970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kvexd-0000w6-AW for importer@patchew.org; Sat, 02 Jan 2021 06:20:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kveqt-0000qA-5e for qemu-devel@nongnu.org; Sat, 02 Jan 2021 06:13:43 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:56507) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kveqp-00077i-M6 for qemu-devel@nongnu.org; Sat, 02 Jan 2021 06:13:42 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 1D917747603; Sat, 2 Jan 2021 12:13:31 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 0D01774760C; Sat, 2 Jan 2021 12:13:30 +0100 (CET) Message-Id: <4d30a2b4b771b2ad651509885daae79d7c4fe7a8.1609584216.git.balaton@eik.bme.hu> In-Reply-To: References: Subject: [PATCH 12/24] vt82c686: Rename superio config related parts Date: Sat, 02 Jan 2021 11:43:35 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: BALATON Zoltan From: BALATON Zoltan via Content-Type: text/plain; charset="utf-8" Use less confusing naming for superio config register handling related parts that makes it clearer what belongs to this part. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/vt82c686.c | 48 +++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 2633cfe7dc..a6f5a0843d 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -27,7 +27,7 @@ #include "trace.h" =20 typedef struct SuperIOConfig { - uint8_t config[0x100]; + uint8_t regs[0x100]; uint8_t index; uint8_t data; } SuperIOConfig; @@ -35,23 +35,23 @@ typedef struct SuperIOConfig { struct VT82C686BISAState { PCIDevice dev; MemoryRegion superio; - SuperIOConfig superio_conf; + SuperIOConfig superio_cfg; }; =20 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) =20 -static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, - unsigned size) +static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) { - SuperIOConfig *superio_conf =3D opaque; + SuperIOConfig *sc =3D opaque; =20 if (addr =3D=3D 0x3f0) { /* config index register */ - superio_conf->index =3D data & 0xff; + sc->index =3D data & 0xff; } else { bool can_write =3D true; /* 0x3f1, config data register */ - trace_via_superio_write(superio_conf->index, data & 0xff); - switch (superio_conf->index) { + trace_via_superio_write(sc->index, data & 0xff); + switch (sc->index) { case 0x00 ... 0xdf: case 0xe4: case 0xe5: @@ -69,23 +69,23 @@ static void superio_ioport_writeb(void *opaque, hwaddr = addr, uint64_t data, =20 } if (can_write) { - superio_conf->config[superio_conf->index] =3D data & 0xff; + sc->regs[sc->index] =3D data & 0xff; } } } =20 -static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned s= ize) +static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) { - SuperIOConfig *superio_conf =3D opaque; - uint8_t val =3D superio_conf->config[superio_conf->index]; + SuperIOConfig *sc =3D opaque; + uint8_t val =3D sc->regs[sc->index]; =20 - trace_via_superio_read(superio_conf->index, val); + trace_via_superio_read(sc->index, val); return val; } =20 -static const MemoryRegionOps superio_ops =3D { - .read =3D superio_ioport_readb, - .write =3D superio_ioport_writeb, +static const MemoryRegionOps superio_cfg_ops =3D { + .read =3D superio_cfg_read, + .write =3D superio_cfg_write, .endianness =3D DEVICE_NATIVE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -112,12 +112,12 @@ static void vt82c686b_isa_reset(DeviceState *dev) pci_conf[0x5f] =3D 0x04; pci_conf[0x77] =3D 0x10; /* GPIO Control 1/2/3/4 */ =20 - s->superio_conf.config[0xe0] =3D 0x3c; - s->superio_conf.config[0xe2] =3D 0x03; - s->superio_conf.config[0xe3] =3D 0xfc; - s->superio_conf.config[0xe6] =3D 0xde; - s->superio_conf.config[0xe7] =3D 0xfe; - s->superio_conf.config[0xe8] =3D 0xbe; + s->superio_cfg.regs[0xe0] =3D 0x3c; /* Device ID */ + s->superio_cfg.regs[0xe2] =3D 0x03; /* Function select */ + s->superio_cfg.regs[0xe3] =3D 0xfc; /* Floppy ctrl base addr */ + s->superio_cfg.regs[0xe6] =3D 0xde; /* Parallel port base addr */ + s->superio_cfg.regs[0xe7] =3D 0xfe; /* Serial port 1 base addr */ + s->superio_cfg.regs[0xe8] =3D 0xbe; /* Serial port 2 base addr */ } =20 /* write config pci function0 registers. PCI-ISA bridge */ @@ -311,8 +311,8 @@ static void vt82c686b_realize(PCIDevice *d, Error **err= p) } } =20 - memory_region_init_io(&s->superio, OBJECT(d), &superio_ops, - &s->superio_conf, "superio", 2); + memory_region_init_io(&s->superio, OBJECT(d), &superio_cfg_ops, + &s->superio_cfg, "superio", 2); memory_region_set_enabled(&s->superio, false); /* * The floppy also uses 0x3f0 and 0x3f1. --=20 2.21.3