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x=1607451395; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eDhmGY3IwRn13ta4fPcQvnOxJ2q4aLyJ5Tn0JitqhXs=; b=rqNoPDJb6/fcvp8Rb+rXK0oh8YS4r03CSX9AA9OOL++ZB4R+m9Ej6chW sg3JLadWv0rszaloBH8RPiNqoGg4b0iien2/JemfstdcnwxHODxWqlElN ieivGGuHiAvUfHhUUPF5Z3oSAMqVNGOSv6IccQAc2aQ+a5z12TZreNXZJ ZOoNLEY8ZDI2XOH6hSIau3VmGxIAUay8/7f/cf6VNoqrX9NHJ55sDDvHg WRWJLJMUAT9xh5LQ7tN8AUy1B2vbyYmiNpXr1vxAiIftOKPO+qFtCpMAk Py0SBRPy7DpLD8SDT9PJ456cLSKTud2hjMmIOuW7MYwIPCj9h85inlAh8 g==; IronPort-SDR: Y/9Jhi9krwgk0CVXaEUcT3TnRzlAljEj5LPF1wm+rXWcI9lu+XTKihCA1U5bHRG9Gx8VnQi3eP 2zgai5bvViw1l7iTHDQ8UdgXytzm51Mzcj64dH04VKHPCFbysT1+JJ2SC9CCeBcsQErLfq5FyV V27hYHhEKA2kjat323UtwdQUnTMGZok011p0j5B9LtOBT/aXYT832CUklnM7yuKwRnta2putS6 fyG6ezMwM3Sm8TWg8IN+0ppBe8vFHmy8MSVuvEQQc6vZ9sPoe++BNJyHSRIfOqdNQvvo+4IPGJ 25s= X-IronPort-AV: E=Sophos;i="5.69,296,1571673600"; d="scan'208";a="126543423" IronPort-SDR: YjzZ3zLMBoEBPELpbhOpEy6e8ExriUADxEqwlKsAX9EEkF5NImjAb6kaF/3ujZIWKZyyJDLc/0 y5wbmTrSiVJD6TFiQucHgyTjhHSQTQbzqcerXzm77wj7cT6o3riblCoU3eZOaDJYvJI2IGh7g5 75MQLJbt1kQI8VHgeTZ5dDl15lCAkfzaXjNbLDnOEqBqANtJlPtXa8YEJJFYOaeKERLTebgDPL YVt28g21/3m2iuIdlUc2p272sxXjuzUAwRXm/iRnly/XyRpogEmWQrdieWgEH0jN6cHHJtNALR OCc8562I5bRW76XpnvJUIWz6 IronPort-SDR: C7Hk5aqiZDPXE19NgLHlo4Eaqimm74bsfCR5nA8Lae8SrvqWBPnDPzx3nDD6BgYa1mhkJglWLA npsd2vWTEl8lwEhDYrEP0AfX6WqC5WPvFjdSrkGLImeuKslo4MvgelpPGkzNIPEc7yyhS1Gsoe ouhbPnjKDmNqpAc+nv+0OJBW7C50wudHKQqixq37RoqoS4FXeQym+ayQXlSolGOxHSx+M6mKNm scaEPFU4v13Ys5cyrZ692GViKWlKMB82pRVkI9sSa4F4Uu03mntLM/a1mG3YEB6gKlM5S1R936 0xk= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 04/36] target/riscv: Add the Hypervisor CSRs to CPUState Date: Mon, 9 Dec 2019 10:10:50 -0800 Message-Id: <4b2d4e889d460e27d8f674d110fd1561768cd035.1575914822.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 21 +++++++++++++++++++++ target/riscv/cpu_bits.h | 34 +++++++++++++++++++++------------- target/riscv/gdbstub.c | 11 ++++++----- 3 files changed, 48 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 91e1c56fc4..bab938103d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -143,6 +143,27 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + /* Hypervisor CSRs */ + target_ulong hstatus; + target_ulong hedeleg; + target_ulong hideleg; + target_ulong hcounteren; + target_ulong htval; + target_ulong htinst; + target_ulong hgatp; + + /* Virtual CSRs */ + target_ulong vsstatus; + target_ulong vstvec; + target_ulong vsscratch; + target_ulong vsepc; + target_ulong vscause; + target_ulong vstval; + target_ulong vsatp; + + target_ulong mtval2; + target_ulong mtinst; + target_ulong scounteren; target_ulong mcounteren; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e99834856c..25c0fb258d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -177,8 +177,14 @@ #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 #define CSR_HIDELEG 0x603 -#define CSR_HCOUNTERNEN 0x606 +#define CSR_HIE 0x604 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HTINST 0x64A #define CSR_HGATP 0x680 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HTIMEDELTAH 0x615 =20 #if defined(TARGET_RISCV32) #define HGATP_MODE SATP32_MODE @@ -191,6 +197,20 @@ #define HGATP_PPN SATP64_PPN #endif =20 +/* Virtual CSRs */ +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 @@ -313,17 +333,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 -/* Legacy Hypervisor Trap Setup (priv v1.9.1) */ -#define CSR_HIE 0x204 -#define CSR_HTVEC 0x205 - -/* Legacy Hypervisor Trap Handling (priv v1.9.1) */ -#define CSR_HSCRATCH 0x240 -#define CSR_HEPC 0x241 -#define CSR_HCAUSE 0x242 -#define CSR_HBADADDR 0x243 -#define CSR_HIP 0x244 - /* Legacy Machine Protection and Translation (priv v1.9.1) */ #define CSR_MBASE 0x380 #define CSR_MBOUND 0x381 @@ -400,7 +409,6 @@ =20 /* hstatus CSR bits */ #define HSTATUS_SPRV 0x00000001 -#define HSTATUS_STL 0x00000040 #define HSTATUS_SPV 0x00000080 #define HSTATUS_SP2P 0x00000100 #define HSTATUS_SP2V 0x00000200 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1a7947e019..6d606f0d90 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -130,6 +130,8 @@ static int csr_register_map[] =3D { CSR_MCAUSE, CSR_MTVAL, CSR_MIP, + CSR_MTINST, + CSR_MTVAL2, CSR_PMPCFG0, CSR_PMPCFG1, CSR_PMPCFG2, @@ -252,12 +254,11 @@ static int csr_register_map[] =3D { CSR_HEDELEG, CSR_HIDELEG, CSR_HIE, - CSR_HTVEC, - CSR_HSCRATCH, - CSR_HEPC, - CSR_HCAUSE, - CSR_HBADADDR, + CSR_HCOUNTEREN, + CSR_HTVAL, CSR_HIP, + CSR_HTINST, + CSR_HGATP, CSR_MBASE, CSR_MBOUND, CSR_MIBASE, --=20 2.24.0