From nobody Mon Feb 9 21:42:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=verisilicon.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1628837101753550.7236090540544; Thu, 12 Aug 2021 23:45:01 -0700 (PDT) Received: from localhost ([::1]:52156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mEQw8-0003G5-7z for importer@patchew.org; Fri, 13 Aug 2021 02:45:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mEQvT-0002be-Pk; Fri, 13 Aug 2021 02:44:20 -0400 Received: from shasxm03.verisilicon.com ([101.89.135.44]:12973) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1mEQvQ-0006A1-DY; Fri, 13 Aug 2021 02:44:19 -0400 Received: from SHASXM06.verisilicon.com ([fe80::59a8:ce34:dc14:ddda]) by SHASXM03.verisilicon.com ([fe80::938:4dda:a2f9:38aa%14]) with mapi id 14.03.0408.000; Fri, 13 Aug 2021 14:44:07 +0800 Content-Language: zh-CN Content-Type: multipart/alternative; boundary="_000_4C23C17B8E87E74E906A25A3254A03F4F216C4FCSHASXM06verisil_" DKIM-Signature: v=1; a=rsa-sha256; d=Verisilicon.com; s=default; c=simple/simple; t=1628837047; h=from:subject:to:date:message-id; bh=JK5UdAj553/f+El6izkKLHjTpl+ITYW2s+9zRZCYc/Q=; b=XEgjJdbumLBJ9IrppE3voWJXdRS9r7/qG0huc/lC9VyknyxHqT85LWBPin69rQOEgJqU4nDWk2j SPjg7r6RBhVwv8NiiDuQN1yCkeQSSo0Y26Y6Q/Q5n9RhDo08tqTrNDUo4fHfSr4HU8MDy6oFjeCwu bzMGTI5AVlk4VEaccnw= From: "Wen, Jianxian" To: "peter.maydell@linaro.org" , "i.mitsyanko@gmail.com" , "edgar.iglesias@gmail.com" , "alistair@alistair23.me" Subject: [PATCH] hw/dma/pl330: Add memory region to replace default address_space_memory Thread-Topic: [PATCH] hw/dma/pl330: Add memory region to replace default address_space_memory Thread-Index: AdeQDpubvwiIcCD2S3W55unV4KNvPA== Date: Fri, 13 Aug 2021 06:44:06 +0000 Message-ID: <4C23C17B8E87E74E906A25A3254A03F4F216C4FC@SHASXM06.verisilicon.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.10.46.67] x-tm-as-product-ver: SMEX-11.0.0.4179-8.100.1062-25628.004 x-tm-as-result: No--24.449300-0.000000-31 x-tm-as-user-approved-sender: Yes x-tm-as-user-blocked-sender: No MIME-Version: 1.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=101.89.135.44; envelope-from=Jianxian.Wen@verisilicon.com; helo=shasxm03.verisilicon.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-arm@nongnu.org" , "Liu, Renwei" , "qemu-devel@nongnu.org" , "Li, Chunming" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1628837103365100001 --_000_4C23C17B8E87E74E906A25A3254A03F4F216C4FCSHASXM06verisil_ Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From f780b0ee2ee36c562ab814915fff0e7217b25e63 Mon Sep 17 00:00:00 2001 From: Jianxian Wen Date: Tue, 3 Aug 2021 09:44:35 +0800 Subject: [PATCH] hw/dma/pl330: Add memory region to replace default address_space_memory PL330 needs a memory region which can connect with SMMU translate IOMMU reg= ion to support SMMU. Signed-off-by: Jianxian Wen --- hw/arm/exynos4210.c | 3 +++ hw/arm/xilinx_zynq.c | 2 ++ hw/dma/pl330.c | 24 ++++++++++++++++++++---- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 5c7a51bba..af0e4820d 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -171,8 +171,11 @@ static DeviceState *pl330_create(uint32_t base, qemu_o= r_irq *orgate, SysBusDevice *busdev; DeviceState *dev; int i; + MemoryRegion *sysmem =3D get_system_memory(); dev =3D qdev_new("pl330"); + object_property_set_link(OBJECT(dev), "memory", + OBJECT(sysmem), &error_fatal); qdev_prop_set_uint8(dev, "num_events", nevents); qdev_prop_set_uint8(dev, "num_chnls", 8); qdev_prop_set_uint8(dev, "num_periph_req", nreq); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 245af81bb..e0b3a73b9 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -312,6 +312,8 @@ static void zynq_init(MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); dev =3D qdev_new("pl330"); + object_property_set_link(OBJECT(dev), "memory", + OBJECT(address_space_mem), &error_fata= l); qdev_prop_set_uint8(dev, "num_chnls", 8); qdev_prop_set_uint8(dev, "num_periph_req", 4); qdev_prop_set_uint8(dev, "num_events", 16); diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index 944ba296b..06747ca0b 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -269,6 +269,9 @@ struct PL330State { uint8_t num_faulting; uint8_t periph_busy[PL330_PERIPH_NUM]; + /* Memory region that DMA operation access */ + MemoryRegion *mem_mr; + AddressSpace mem_as; }; #define TYPE_PL330 "pl330" @@ -1108,7 +1111,8 @@ static inline const PL330InsnDesc *pl330_fetch_insn(P= L330Chan *ch) uint8_t opcode; int i; - dma_memory_read(&address_space_memory, ch->pc, &opcode, 1); + address_space_read(&ch->parent->mem_as, ch->pc, + MEMTXATTRS_UNSPECIFIED, &opcode, 1); for (i =3D 0; insn_desc[i].size; i++) { if ((opcode & insn_desc[i].opmask) =3D=3D insn_desc[i].opcode) { return &insn_desc[i]; @@ -1122,7 +1126,8 @@ static inline void pl330_exec_insn(PL330Chan *ch, con= st PL330InsnDesc *insn) uint8_t buf[PL330_INSN_MAXSIZE]; assert(insn->size <=3D PL330_INSN_MAXSIZE); - dma_memory_read(&address_space_memory, ch->pc, buf, insn->size); + address_space_read(&ch->parent->mem_as, ch->pc, + MEMTXATTRS_UNSPECIFIED, buf, insn->size); insn->exec(ch, buf[0], &buf[1], insn->size - 1); } @@ -1186,7 +1191,8 @@ static int pl330_exec_cycle(PL330Chan *channel) if (q !=3D NULL && q->len <=3D pl330_fifo_num_free(&s->fifo)) { int len =3D q->len - (q->addr & (q->len - 1)); - dma_memory_read(&address_space_memory, q->addr, buf, len); + address_space_read(&s->mem_as, q->addr, + MEMTXATTRS_UNSPECIFIED, buf, len); trace_pl330_exec_cycle(q->addr, len); if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { pl330_hexdump(buf, len); @@ -1217,7 +1223,8 @@ static int pl330_exec_cycle(PL330Chan *channel) fifo_res =3D pl330_fifo_get(&s->fifo, buf, len, q->tag); } if (fifo_res =3D=3D PL330_FIFO_OK || q->z) { - dma_memory_write(&address_space_memory, q->addr, buf, len); + address_space_write(&s->mem_as, q->addr, + MEMTXATTRS_UNSPECIFIED, buf, len); trace_pl330_exec_cycle(q->addr, len); if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { pl330_hexdump(buf, len); @@ -1562,6 +1569,12 @@ static void pl330_realize(DeviceState *dev, Error **= errp) "dma", PL330_IOMEM_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + if (!s->mem_mr) { + error_setg(errp, "'mem_mr' link is not set"); + return; + } + address_space_init(&s->mem_as, s->mem_mr, "pl330-memory"); + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, = s); s->cfg[0] =3D (s->mgr_ns_at_rst ? 0x4 : 0) | @@ -1656,6 +1669,9 @@ static Property pl330_properties[] =3D { DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16), DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256= ), + DEFINE_PROP_LINK("memory", PL330State, mem_mr, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), }; -- --_000_4C23C17B8E87E74E906A25A3254A03F4F216C4FCSHASXM06verisil_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

From f780b0ee2ee36c562ab814915f= ff0e7217b25e63 Mon Sep 17 00:00:00 2001

From: Jianxian Wen <jianxian= .wen@verisilicon.com>

Date: Tue, 3 Aug 2021 09:44:35 = +0800

Subject: [PATCH] hw/dma/pl330: = Add memory region to replace default

 address_space_memory=

 

PL330 needs a memory region whi= ch can connect with SMMU translate IOMMU region to support SMMU.=

 

Signed-off-by: Jianxian Wen <= ;jianxian.wen@verisilicon.com>

---

 hw/arm/exynos4210.c = |  3 +++

 hw/arm/xilinx_zynq.c |&nb= sp; 2 ++

 hw/dma/pl330.c  = ;     | 24 +++++++++= ;+++++++++++----

 3 files changed, 25 inser= tions(+), 4 deletions(-)

 

diff --git a/hw/arm/exynos4210.= c b/hw/arm/exynos4210.c

index 5c7a51bba..af0e4820d 1006= 44

--- a/hw/arm/exynos4210.c<= /o:p>

+++ b/hw/arm/exynos= 4210.c

@@ -171,8 +171,11 @@ static= DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,

     SysBus= Device *busdev;

     Device= State *dev;

     int i;=

+    MemoryR= egion *sysmem =3D get_system_memory();

 

     dev = =3D qdev_new("pl330");

+    object_= property_set_link(OBJECT(dev), "memory",

+    &n= bsp;            = ;            &n= bsp;      OBJECT(sysmem), &error_fatal);<= /o:p>

     qdev_p= rop_set_uint8(dev, "num_events", nevents);

     qdev_p= rop_set_uint8(dev, "num_chnls",  8);

     qdev_p= rop_set_uint8(dev, "num_periph_req",  nreq);

diff --git a/hw/arm/xilinx_zynq= .c b/hw/arm/xilinx_zynq.c

index 245af81bb..e0b3a73b9 1006= 44

--- a/hw/arm/xilinx_zynq.c=

+++ b/hw/arm/xilinx= _zynq.c

@@ -312,6 +312,8 @@ static = void zynq_init(MachineState *machine)

     sysbus= _connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);=

 

     dev = =3D qdev_new("pl330");

+    object_= property_set_link(OBJECT(dev), "memory",

+    &n= bsp;            = ;            &n= bsp;      OBJECT(address_space_mem), &error_fa= tal);

     qdev_p= rop_set_uint8(dev, "num_chnls",  8);

     qdev_p= rop_set_uint8(dev, "num_periph_req",  4);<= /p>

     qdev_p= rop_set_uint8(dev, "num_events",  16);

diff --git a/hw/dma/pl330.c b/h= w/dma/pl330.c

index 944ba296b..06747ca0b 1006= 44

--- a/hw/dma/pl330.c=

+++ b/hw/dma/pl330.= c

@@ -269,6 +269,9 @@ struct = PL330State {

     uint8_= t num_faulting;

     uint8_= t periph_busy[PL330_PERIPH_NUM];

 

+    /* Memo= ry region that DMA operation access */

+    MemoryR= egion *mem_mr;

+    Address= Space mem_as;

 };

 

 #define TYPE_PL330 "= pl330"

@@ -1108,7 +1111,8 @@ stati= c inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch)

     uint8_= t opcode;

     int i;=

 

-    dma_memory_= read(&address_space_memory, ch->pc, &opcode, 1);

+    address= _space_read(&ch->parent->mem_as, ch->pc,

+    &n= bsp;            = ;       MEMTXATTRS_UNSPECIFIED, &opcode, = 1);

     for (i= =3D 0; insn_desc[i].size; i++) {

     &= nbsp;   if ((opcode & insn_desc[i].opmask) =3D=3D insn_desc[i= ].opcode) {

     &= nbsp;       return &insn_desc[i];

@@ -1122,7 +1126,8 @@ stati= c inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn)

     uint8_= t buf[PL330_INSN_MAXSIZE];

 

     assert= (insn->size <=3D PL330_INSN_MAXSIZE);

-    dma_memory_= read(&address_space_memory, ch->pc, buf, insn->size);<= /span>

+    address= _space_read(&ch->parent->mem_as, ch->pc,

+    &n= bsp;            &nbs= p;      MEMTXATTRS_UNSPECIFIED, buf, insn->= ;size);

     insn-&= gt;exec(ch, buf[0], &buf[1], insn->size - 1);

 }

 

@@ -1186,7 +1191,8 @@ stati= c int pl330_exec_cycle(PL330Chan *channel)

     if (q = !=3D NULL && q->len <=3D pl330_fifo_num_free(&s->fifo)= ) {

     &= nbsp;   int len =3D q->len - (q->addr & (q->len - 1)= );

 

-     =    dma_memory_read(&address_space_memory, q->addr, buf, le= n);

+    &n= bsp;   address_space_read(&s->mem_as, q->addr,

+    &n= bsp;            = ;           MEMTXATTRS_UN= SPECIFIED, buf, len);

     &= nbsp;   trace_pl330_exec_cycle(q->addr, len);

     &= nbsp;   if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) = {

     &= nbsp;       pl330_hexdump(buf, len);

@@ -1217,7 +1223,8 @@ stati= c int pl330_exec_cycle(PL330Chan *channel)

     &= nbsp;       fifo_res =3D pl330_fifo_get(&= s->fifo, buf, len, q->tag);

     &= nbsp;   }

     &= nbsp;   if (fifo_res =3D=3D PL330_FIFO_OK || q->z) {

-     =        dma_memory_write(&address_space_me= mory, q->addr, buf, len);

+    &n= bsp;       address_space_write(&s->mem= _as, q->addr,

+    &n= bsp;            = ;            &n= bsp;  MEMTXATTRS_UNSPECIFIED, buf, len);

     &= nbsp;       trace_pl330_exec_cycle(q->addr= , len);

     &= nbsp;       if (trace_event_get_state_backend= s(TRACE_PL330_HEXDUMP)) {

     &= nbsp;           pl330_hex= dump(buf, len);

@@ -1562,6 +1569,12 @@ stat= ic void pl330_realize(DeviceState *dev, Error **errp)

     &= nbsp;           &nbs= p;         "dma", PL330_I= OMEM_SIZE);

     sysbus= _init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);

 

+    if (!s-= >mem_mr) {

+    &n= bsp;   error_setg(errp, "'mem_mr' link is not set");

+    &n= bsp;   return;

+    }<= /o:p>

+    address= _space_init(&s->mem_as, s->mem_mr, "pl330-memory");

+

     s->= timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s);=

 

     s->= cfg[0] =3D (s->mgr_ns_at_rst ? 0x4 : 0) |

@@ -1656,6 +1669,9 @@ stati= c Property pl330_properties[] =3D {

     DEFINE= _PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16),

     DEFINE= _PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256)= ,

 

+    DEFINE_= PROP_LINK("memory", PL330State, mem_mr,

+    &n= bsp;            = ;    TYPE_MEMORY_REGION, MemoryRegion *),<= /p>

+

     DEFINE= _PROP_END_OF_LIST(),

 };

 

--

--_000_4C23C17B8E87E74E906A25A3254A03F4F216C4FCSHASXM06verisil_--