From nobody Wed Nov 5 17:47:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496748801152146.02640217317924; Tue, 6 Jun 2017 04:33:21 -0700 (PDT) Received: from localhost ([::1]:37656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICjc-0004KY-AK for importer@patchew.org; Tue, 06 Jun 2017 07:33:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43936) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICev-0000VS-MA for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dICep-0002lc-1H for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:24 -0400 Received: from [59.151.112.132] (port=55441 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICeo-0002g4-9x for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:18 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 06 Jun 2017 19:28:01 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id 56AAB47C7C69; Tue, 6 Jun 2017 19:27:57 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Jun 2017 19:27:56 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716139" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:32 +0800 Message-ID: <4842dd61954d23862cf834a00847376bc54fb4da.1496746391.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: 56AAB47C7C69.A4897 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 7/7] pci: Convert shpc_init() to Error X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, armbru@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to propagate error message better, convert shpc_init() to Error also convert the pci_bridge_dev_initfn() to realize. Cc: mst@redhat.com Cc: marcel@redhat.com Cc: armbru@redhat.com Signed-off-by: Mao Zhongyi --- hw/pci-bridge/pci_bridge_dev.c | 21 ++++++++------------- hw/pci/shpc.c | 11 +++++------ hw/pci/slotid_cap.c | 11 +++++------ include/hw/pci/shpc.h | 3 ++- include/hw/pci/slotid_cap.h | 3 ++- 5 files changed, 22 insertions(+), 27 deletions(-) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 5dbd933..30c4186 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -49,12 +49,11 @@ struct PCIBridgeDev { }; typedef struct PCIBridgeDev PCIBridgeDev; =20 -static int pci_bridge_dev_initfn(PCIDevice *dev) +static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp) { PCIBridge *br =3D PCI_BRIDGE(dev); PCIBridgeDev *bridge_dev =3D PCI_BRIDGE_DEV(dev); int err; - Error *local_err =3D NULL; =20 pci_bridge_initfn(dev, TYPE_PCI_BUS); =20 @@ -62,7 +61,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) dev->config[PCI_INTERRUPT_PIN] =3D 0x1; memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev)); - err =3D shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0); + err =3D shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp); if (err) { goto shpc_error; } @@ -71,7 +70,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) bridge_dev->msi =3D ON_OFF_AUTO_OFF; } =20 - err =3D slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0); + err =3D slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0, errp); if (err) { goto slotid_error; } @@ -79,20 +78,18 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) if (bridge_dev->msi !=3D ON_OFF_AUTO_OFF) { /* it means SHPC exists, because MSI is needed by SHPC */ =20 - err =3D msi_init(dev, 0, 1, true, true, &local_err); + err =3D msi_init(dev, 0, 1, true, true, errp); /* Any error other than -ENOTSUP(board's MSI support is broken) * is a programming error */ assert(!err || err =3D=3D -ENOTSUP); if (err && bridge_dev->msi =3D=3D ON_OFF_AUTO_ON) { /* Can't satisfy user's explicit msi=3Don request, fail */ - error_append_hint(&local_err, "You have to use msi=3Dauto (def= ault) " + error_append_hint(errp, "You have to use msi=3Dauto (default) " "or msi=3Doff with this machine type.\n"); - error_report_err(local_err); goto msi_error; } - assert(!local_err || bridge_dev->msi =3D=3D ON_OFF_AUTO_AUTO); + assert(bridge_dev->msi =3D=3D ON_OFF_AUTO_AUTO); /* With msi=3Dauto, we fall back to MSI off silently */ - error_free(local_err); } =20 if (shpc_present(dev)) { @@ -101,7 +98,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar); } - return 0; + return; =20 msi_error: slotid_cap_cleanup(dev); @@ -111,8 +108,6 @@ slotid_error: } shpc_error: pci_bridge_exitfn(dev); - - return err; } =20 static void pci_bridge_dev_exitfn(PCIDevice *dev) @@ -216,7 +211,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klas= s, void *data) PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); =20 - k->init =3D pci_bridge_dev_initfn; + k->realize =3D pci_bridge_dev_realize; k->exit =3D pci_bridge_dev_exitfn; k->config_write =3D pci_bridge_dev_write_config; k->vendor_id =3D PCI_VENDOR_ID_REDHAT; diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index d72d5e4..69fc14b 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -446,16 +446,14 @@ static void shpc_cap_update_dword(PCIDevice *d) } =20 /* Add SHPC capability to the config space for the device. */ -static int shpc_cap_add_config(PCIDevice *d) +static int shpc_cap_add_config(PCIDevice *d, Error **errp) { uint8_t *config; int config_offset; - Error *local_err =3D NULL; config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, 0, SHPC_CAP_LENGTH, - &local_err); + errp); if (config_offset < 0) { - error_report_err(local_err); return config_offset; } config =3D d->config + config_offset; @@ -584,13 +582,14 @@ void shpc_device_hot_unplug_request_cb(HotplugHandler= *hotplug_dev, } =20 /* Initialize the SHPC structure in bridge's BAR. */ -int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned o= ffset) +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, + unsigned offset, Error **errp) { int i, ret; int nslots =3D SHPC_MAX_SLOTS; /* TODO: qdev property? */ SHPCDevice *shpc =3D d->shpc =3D g_malloc0(sizeof(*d->shpc)); shpc->sec_bus =3D sec_bus; - ret =3D shpc_cap_add_config(d); + ret =3D shpc_cap_add_config(d, errp); if (ret) { g_free(d->shpc); return ret; diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c index bdca205..36d021b 100644 --- a/hw/pci/slotid_cap.c +++ b/hw/pci/slotid_cap.c @@ -9,14 +9,14 @@ =20 int slotid_cap_init(PCIDevice *d, int nslots, uint8_t chassis, - unsigned offset) + unsigned offset, + Error **errp) { int cap; - Error *local_err =3D NULL; =20 if (!chassis) { - error_report("Bridge chassis not specified. Each bridge is require= d " - "to be assigned a unique chassis id > 0."); + error_setg(errp, "Bridge chassis not specified. Each bridge is req= uired" + " to be assigned a unique chassis id > 0."); return -EINVAL; } if (nslots < 0 || nslots > (PCI_SID_ESR_NSLOTS >> SLOTID_NSLOTS_SHIFT)= ) { @@ -25,9 +25,8 @@ int slotid_cap_init(PCIDevice *d, int nslots, } =20 cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, - SLOTID_CAP_LENGTH, &local_err); + SLOTID_CAP_LENGTH, errp); if (cap < 0) { - error_report_err(local_err); return cap; } /* We make each chassis unique, this way each bridge is First in Chass= is */ diff --git a/include/hw/pci/shpc.h b/include/hw/pci/shpc.h index b208554..1ea88b1 100644 --- a/include/hw/pci/shpc.h +++ b/include/hw/pci/shpc.h @@ -39,7 +39,8 @@ struct SHPCDevice { =20 void shpc_reset(PCIDevice *d); int shpc_bar_size(PCIDevice *dev); -int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned= off); +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, + unsigned off, Error **errp); void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar); void shpc_free(PCIDevice *dev); void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int = len); diff --git a/include/hw/pci/slotid_cap.h b/include/hw/pci/slotid_cap.h index 70db047..a777ea0 100644 --- a/include/hw/pci/slotid_cap.h +++ b/include/hw/pci/slotid_cap.h @@ -5,7 +5,8 @@ =20 int slotid_cap_init(PCIDevice *dev, int nslots, uint8_t chassis, - unsigned offset); + unsigned offset, + Error **errp); void slotid_cap_cleanup(PCIDevice *dev); =20 #endif --=20 2.9.3