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Sun, 20 Aug 2017 13:48:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1djUKw-00055A-O6 for qemu-devel@nongnu.org; Sun, 20 Aug 2017 13:48:36 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:27152) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1djUKw-00053k-A6; Sun, 20 Aug 2017 13:48:34 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id CACAA747DDE; Sun, 20 Aug 2017 19:48:31 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 39531747DBF; Sun, 20 Aug 2017 19:48:31 +0200 (CEST) Message-Id: <4817dda8eabbba2c7a3c886a1f70b7872ce8ae31.1503249785.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Sun, 20 Aug 2017 19:23:05 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH 06/15] ppc4xx_i2c: QOMify X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Francois Revol , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 2 - hw/ppc/ppc405_uc.c | 5 +- hw/ppc/ppc4xx_i2c.c | 154 ++++++++++++++--------------------------= ---- include/hw/i2c/ppc4xx_i2c.h | 61 ++++++++++++++++++ 4 files changed, 113 insertions(+), 109 deletions(-) create mode 100644 include/hw/i2c/ppc4xx_i2c.h diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 61ec739..a9ffc87 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -59,8 +59,6 @@ struct ppc4xx_bd_info_t { ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags); =20 -void ppc405_i2c_init(hwaddr base, qemu_irq irq); - CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[4], hwaddr ram_bases[4], diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3925e4c..8f44cb4 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -28,6 +28,7 @@ #include "hw/hw.h" #include "hw/ppc/ppc.h" #include "hw/boards.h" +#include "hw/i2c/ppc4xx_i2c.h" #include "ppc405.h" #include "hw/char/serial.h" #include "qemu/timer.h" @@ -1663,7 +1664,7 @@ CPUPPCState *ppc405cr_init(MemoryRegion *address_spac= e_mem, DEVICE_BIG_ENDIAN); } /* IIC controller */ - ppc405_i2c_init(0xef600500, pic[2]); + sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); /* GPIO */ ppc405_gpio_init(0xef600700); /* CPU control */ @@ -2010,7 +2011,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_spac= e_mem, dma_irqs[3] =3D pic[8]; ppc405_dma_init(env, dma_irqs); /* IIC controller */ - ppc405_i2c_init(0xef600500, pic[2]); + sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); /* GPIO */ ppc405_gpio_init(0xef600700); /* Serial ports */ diff --git a/hw/ppc/ppc4xx_i2c.c b/hw/ppc/ppc4xx_i2c.c index 15f2dea..5a6bde9 100644 --- a/hw/ppc/ppc4xx_i2c.c +++ b/hw/ppc/ppc4xx_i2c.c @@ -27,42 +27,20 @@ #include "qemu-common.h" #include "cpu.h" #include "hw/hw.h" -#include "exec/address-spaces.h" -#include "hw/ppc/ppc.h" -#include "ppc405.h" +#include "hw/i2c/ppc4xx_i2c.h" =20 /*#define DEBUG_I2C*/ =20 -typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; -struct ppc4xx_i2c_t { - qemu_irq irq; - MemoryRegion iomem; - uint8_t mdata; - uint8_t lmadr; - uint8_t hmadr; - uint8_t cntl; - uint8_t mdcntl; - uint8_t sts; - uint8_t extsts; - uint8_t sdata; - uint8_t lsadr; - uint8_t hsadr; - uint8_t clkdiv; - uint8_t intrmsk; - uint8_t xfrcnt; - uint8_t xtcntlss; - uint8_t directcntl; -}; +#define PPC4xx_I2C_MEM_SIZE 0x11 =20 -static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr addr) +static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int s= ize) { - ppc4xx_i2c_t *i2c; - uint32_t ret; + PPC4xxI2CState *i2c =3D PPC4xx_I2C(opaque); + uint64_t ret; =20 #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); #endif - i2c =3D opaque; switch (addr) { case 0x00: /*i2c_readbyte(&i2c->mdata);*/ @@ -115,22 +93,20 @@ static uint32_t ppc4xx_i2c_readb(void *opaque, hwaddr = addr) break; } #ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, = ret); + printf("%s: addr " TARGET_FMT_plx " %02" PRIx64 "\n", __func__, addr, = ret); #endif =20 return ret; } =20 -static void ppc4xx_i2c_writeb(void *opaque, - hwaddr addr, uint32_t value) +static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) { - ppc4xx_i2c_t *i2c; - + PPC4xxI2CState *i2c =3D opaque; #ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, ad= dr, - value); + printf("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", + __func__, addr, value); #endif - i2c =3D opaque; switch (addr) { case 0x00: i2c->mdata =3D value; @@ -181,71 +157,20 @@ static void ppc4xx_i2c_writeb(void *opaque, } } =20 -static uint32_t ppc4xx_i2c_readw(void *opaque, hwaddr addr) -{ - uint32_t ret; - -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - ret =3D ppc4xx_i2c_readb(opaque, addr) << 8; - ret |=3D ppc4xx_i2c_readb(opaque, addr + 1); - - return ret; -} - -static void ppc4xx_i2c_writew(void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, ad= dr, - value); -#endif - ppc4xx_i2c_writeb(opaque, addr, value >> 8); - ppc4xx_i2c_writeb(opaque, addr + 1, value); -} - -static uint32_t ppc4xx_i2c_readl(void *opaque, hwaddr addr) -{ - uint32_t ret; - -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - ret =3D ppc4xx_i2c_readb(opaque, addr) << 24; - ret |=3D ppc4xx_i2c_readb(opaque, addr + 1) << 16; - ret |=3D ppc4xx_i2c_readb(opaque, addr + 2) << 8; - ret |=3D ppc4xx_i2c_readb(opaque, addr + 3); - - return ret; -} - -static void ppc4xx_i2c_writel(void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, ad= dr, - value); -#endif - ppc4xx_i2c_writeb(opaque, addr, value >> 24); - ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); - ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); - ppc4xx_i2c_writeb(opaque, addr + 3, value); -} - -static const MemoryRegionOps i2c_ops =3D { - .old_mmio =3D { - .read =3D { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, = }, - .write =3D { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writ= el, }, - }, +static const MemoryRegionOps ppc4xx_i2c_ops =3D { + .read =3D ppc4xx_i2c_readb, + .write =3D ppc4xx_i2c_writeb, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 1, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void ppc4xx_i2c_reset(void *opaque) +static void ppc4xx_i2c_reset(DeviceState *s) { - ppc4xx_i2c_t *i2c; + PPC4xxI2CState *i2c =3D PPC4xx_I2C(s); =20 - i2c =3D opaque; i2c->mdata =3D 0x00; i2c->sdata =3D 0x00; i2c->cntl =3D 0x00; @@ -257,16 +182,35 @@ static void ppc4xx_i2c_reset(void *opaque) i2c->directcntl =3D 0x0F; } =20 -void ppc405_i2c_init(hwaddr base, qemu_irq irq) +static void ppc4xx_i2c_init(Object *o) { - ppc4xx_i2c_t *i2c; + PPC4xxI2CState *s =3D PPC4xx_I2C(o); =20 - i2c =3D g_malloc0(sizeof(ppc4xx_i2c_t)); - i2c->irq =3D irq; -#ifdef DEBUG_I2C - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif - memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011); - memory_region_add_subregion(get_system_memory(), base, &i2c->iomem); - qemu_register_reset(ppc4xx_i2c_reset, i2c); + memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s, + TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); + s->bus =3D i2c_init_bus(DEVICE(s), "i2c"); } + +static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D ppc4xx_i2c_reset; +} + +static const TypeInfo ppc4xx_i2c_type_info =3D { + .name =3D TYPE_PPC4xx_I2C, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(PPC4xxI2CState), + .instance_init =3D ppc4xx_i2c_init, + .class_init =3D ppc4xx_i2c_class_init, +}; + +static void ppc4xx_i2c_register_types(void) +{ + type_register_static(&ppc4xx_i2c_type_info); +} + +type_init(ppc4xx_i2c_register_types) diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h new file mode 100644 index 0000000..e53042f --- /dev/null +++ b/include/hw/i2c/ppc4xx_i2c.h @@ -0,0 +1,61 @@ +/* + * PPC4xx I2C controller emulation + * + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef PPC4XX_I2C_H +#define PPC4XX_I2C_H + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hw/sysbus.h" +#include "hw/i2c/i2c.h" + +#define TYPE_PPC4xx_I2C "ppc4xx-i2c" +#define PPC4xx_I2C(obj) OBJECT_CHECK(PPC4xxI2CState, (obj), TYPE_PPC4xx_I2= C) + +typedef struct PPC4xxI2CState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + I2CBus *bus; + qemu_irq irq; + MemoryRegion iomem; + uint8_t mdata; + uint8_t lmadr; + uint8_t hmadr; + uint8_t cntl; + uint8_t mdcntl; + uint8_t sts; + uint8_t extsts; + uint8_t sdata; + uint8_t lsadr; + uint8_t hsadr; + uint8_t clkdiv; + uint8_t intrmsk; + uint8_t xfrcnt; + uint8_t xtcntlss; + uint8_t directcntl; +} PPC4xxI2CState; + +#endif /* PPC4XX_I2C_H */ --=20 2.7.6