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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 79966ac6e6..275b6c2a67 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -296,10 +296,19 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ul= ong newpriv) * * Adapted from Spike's mmu_t::translate and mmu_t::walk * + * @env: CPURISCVState + * @physical: This will be set to the calculated physical address + * @prot: The returned protection attributes + * @addr: The virtual address to be translated + * @access_type: The type of MMU access + * @mmu_idx: Indicates current privilege level + * @first_stage: Are we in first stage translation? + * Second stage is used for hypervisor guest translation */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *prot, target_ulong addr, - int access_type, int mmu_idx) + int access_type, int mmu_idx, + bool first_stage) { /* NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler @@ -502,13 +511,23 @@ restart: } =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, - MMUAccessType access_type, bool pmp_violat= ion) + MMUAccessType access_type, bool pmp_violat= ion, + bool first_stage) { CPUState *cs =3D env_cpu(env); - int page_fault_exceptions =3D - (env->priv_ver >=3D PRIV_VERSION_1_10_0) && - get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && - !pmp_violation; + int page_fault_exceptions; + if (first_stage) { + page_fault_exceptions =3D + (env->priv_ver >=3D PRIV_VERSION_1_10_0) && + get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && + !pmp_violation; + riscv_cpu_set_force_hs_excep(env, 0); + } else { + page_fault_exceptions =3D + get_field(env->hgatp, HGATP_MODE) !=3D VM_1_10_MBARE && + !pmp_violation; + riscv_cpu_set_force_hs_excep(env, 1); + } switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D page_fault_exceptions ? @@ -535,7 +554,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) int prot; int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_id= x)) { + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_id= x, + true)) { return -1; } return phys_addr; @@ -601,7 +621,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx); + ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx, + true); =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(*env->mstatus, MSTATUS_MPRV)) { @@ -638,7 +659,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation); + raise_mmu_exception(env, address, access_type, pmp_violation, true= ); riscv_raise_exception(env, cs->exception_index, retaddr); } #else --=20 2.23.0