From nobody Thu Nov 6 10:23:02 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540490373099583.216861613774; Thu, 25 Oct 2018 10:59:33 -0700 (PDT) Received: from localhost ([::1]:56214 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFjur-0002N4-VD for importer@patchew.org; Thu, 25 Oct 2018 13:59:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFjUO-0007OH-JM for qemu-devel@nongnu.org; Thu, 25 Oct 2018 13:32:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFjUL-0007qr-8F for qemu-devel@nongnu.org; Thu, 25 Oct 2018 13:32:08 -0400 Received: from pio-pvt-msa2.bahnhof.se ([79.136.2.41]:40879) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFjUK-0007lu-T7 for qemu-devel@nongnu.org; Thu, 25 Oct 2018 13:32:05 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTP id 63CBD3F6A6; Thu, 25 Oct 2018 19:32:03 +0200 (CEST) Received: from pio-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WoNcBt1-IeT5; Thu, 25 Oct 2018 19:31:58 +0200 (CEST) Received: from localhost (h-41-252.A163.priv.bahnhof.se [46.59.41.252]) (Authenticated sender: mb547485) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id 201AE3F59D; Thu, 25 Oct 2018 19:31:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se Date: Thu, 25 Oct 2018 19:31:57 +0200 From: Fredrik Noring To: Aleksandar Markovic , Aurelien Jarno , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Message-ID: <46516cbad6912c9592b439b4e32986c5ed7fa527.1540487815.git.noring@nocrew.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.41 Subject: [Qemu-devel] [PATCH 03/11] target/mips: Support Toshiba specific three-operand MADD and MADDU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?Q?J=C3=BCrgen?= Urban , qemu-devel@nongnu.org, "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Philippe Mathieu-Daud=C3=A9 The three-operand MADD and MADDU are specific to the Toshiba TX19/TX39/TX79 cores. The "32-Bit TX System RISC TX39 Family Architecture manual" is available at https://wiki.qemu.org/File:DSAE0022432.pdf Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Fredrik Noring Tested-by: Fredrik Noring --- target/mips/translate.c | 58 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 18167df26d..add6203c5a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4801,8 +4801,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, } =20 /* - * These MULT and MULTU instructions implemented in for example the - * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core + * These MULT[U] and MADD[U] instructions implemented in for example + * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core * architectures are special three-operand variants with the syntax * * MULT[U][1] rd, rs, rt @@ -4811,6 +4811,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t o= pc, * * (rd, LO, HI) <- rs * rt * + * and + * + * MADD[U] rd, rs, rt + * + * such that + * + * (rd, LO, HI) <- (LO, HI) + rs * rt + * * where the low-order 32-bits of the result is placed into both the * GPR rd and the special register LO. The high-order 32-bits of the * result is placed into the special register HI. @@ -4867,8 +4875,48 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t= opc, tcg_temp_free_i32(t3); } break; + case TX79_MMI_MADD: + { + TCGv_i64 t2 =3D tcg_temp_new_i64(); + TCGv_i64 t3 =3D tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); + if (rd) { + gen_move_low32(cpu_gpr[rd], t2); + } + tcg_temp_free_i64(t2); + } + break; + case TX79_MMI_MADDU: + { + TCGv_i64 t2 =3D tcg_temp_new_i64(); + TCGv_i64 t3 =3D tcg_temp_new_i64(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); + if (rd) { + gen_move_low32(cpu_gpr[rd], t2); + } + tcg_temp_free_i64(t2); + } + break; default: - MIPS_INVAL("mul TXx9"); + MIPS_INVAL("mul/madd TXx9"); generate_exception_end(ctx, EXCP_RI); goto out; } @@ -24699,6 +24747,8 @@ static void decode_tx79_mmi(CPUMIPSState *env, Disa= sContext *ctx) break; case TX79_MMI_MULT1: case TX79_MMI_MULTU1: + case TX79_MMI_MADD: + case TX79_MMI_MADDU: gen_mul_txx9(ctx, opc, rd, rs, rt); break; case TX79_MMI_DIV1: @@ -24713,8 +24763,6 @@ static void decode_tx79_mmi(CPUMIPSState *env, Disa= sContext *ctx) case TX79_MMI_MFHI1: gen_HILO(ctx, opc, 1, rd); break; - case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */ - case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */ case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */ case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */ case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */ --=20 2.18.1