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[124.44.183.209]) by smtp.gmail.com with ESMTPSA id r18sm495219pfk.109.2017.05.03.17.53.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2017 17:53:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=9mCr71zRIanCxE320hbzHVdcvw954RnaCnMU5tfyVf8=; b=uXFaWGE18qltRrk5JWjArvjcYDMnzTUJX6LhvAFEfu3W/FACAnql9T18u+rynQyhLT eJDO7zyAMN11+xFw8t0jT3at0Y3oiFIW8ZAQaaiVIW9JxbMyO38XkVqCsosGHDO46Kqo 0wukTzI7TVltJ+ALmapZGCF9mRoB2lmQDZDyBQRvhVahsTo/MTWNOeVvT6cfu6tUvgR/ vtjcAi+ToGgOPMfin8z9fEbgSMRG13mR1r/9RlHB2syTDPwqr9coJrvKQqe7eZCO+fh5 zSceTZk8Okz2hc+rk4lifT4iCrcC9BUAHkHyou5EuhM1sqr2Wv0z0SLQMVOPIiKD7dVA t7qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=9mCr71zRIanCxE320hbzHVdcvw954RnaCnMU5tfyVf8=; b=DQwSheLfXZd4uEQVxTFuMBghHHg4/Gf041HWtAnfyQRvjRkYviNuAQEMmUzb5JU2hQ XsS3ENHi9MeVfWYtpQUF6eH6yqM32e43ePs3ZF+6xNj2L0Ro7VtNckXUHiJOofwLMKP7 bN1YzPPvdl/+c/ioKGZJ8c5QnxTfnDvG9MWxG1V/L4jPG4Z1nyuBhr7FHE6+eG9nH5A1 Z8Y17sGwC58LO2CS6WDBZ1thi7h/fCOBbbAYwmUVPhnttAGU5PQcMATBF1fAIFH2PmNi s6J7T+38pq9Py1RgfgPewzC8jUwQWp0dEhbPPxs02IyfTvPdrqVyNIBdoK/bCT/BbUAk ndQw== X-Gm-Message-State: AN3rC/5VDyD/gcihPDrJIrCt/k7rh1RJfsqUf7kL4zwTPTULrRkYzc5I r6ni3xY2h077Hw== X-Received: by 10.84.198.3 with SMTP id o3mr51952785pld.45.1493859231251; Wed, 03 May 2017 17:53:51 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Thu, 4 May 2017 09:53:19 +0900 Message-Id: <461a4b944f7e036b2f6bd1fce83ad4fe09e5e2bc.1493858877.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL v2 04/11] target/openrisc: Fixes for memory debugging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When debugging in gdb you might want to inspect instructions in mapped pages or in exception vectors like 0x800 etc. This was previously not possible in qemu since the *get_phys_page_debug() routine only looked into the data tlb. Change to fall back to look into instruction tlb and plain physical pages. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/mmu.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 56b11d3..ce2a29d 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -124,7 +124,7 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, { int ret =3D TLBRET_MATCH; =20 - if (rw =3D=3D 2) { /* ITLB */ + if (rw =3D=3D MMU_INST_FETCH) { /* ITLB */ *physical =3D 0; ret =3D cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical, prot, address, r= w); @@ -221,12 +221,28 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs,= vaddr addr) OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); hwaddr phys_addr; int prot; + int miss; =20 - if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) { - return -1; + /* Check memory for any kind of address, since during debug the + gdb can ask for anything, check data tlb for address */ + miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + + /* Check instruction tlb */ + if (miss) { + miss =3D cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, + MMU_INST_FETCH); + } + + /* Last, fall back to a plain address */ + if (miss) { + miss =3D cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr,= 0); } =20 - return phys_addr; + if (miss) { + return -1; + } else { + return phys_addr; + } } =20 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) --=20 2.9.3