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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775127010275158500 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point arithmetic instructions: - vmpy_sf_sf, vmpy_sf_hf, vmpy_hf_hf: multiply operations - vdmpy_sf_hf: dot-product multiply - vmpy_sf_hf_acc, vmpy_hf_hf_acc, vdmpy_sf_hf_acc: multiply-accumulate - vadd_sf_sf, vsub_sf_sf, vadd_sf_hf, vsub_sf_hf: add/sub with sf output - vadd_hf_hf, vsub_hf_hf: add/sub with hf output Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.h | 1 + target/hexagon/mmvec/hvx_ieee_fp.h | 47 ++++++++++ target/hexagon/mmvec/macros.h | 1 + target/hexagon/mmvec/mmvec.h | 2 + target/hexagon/attribs_def.h.inc | 4 + target/hexagon/arch.c | 8 ++ target/hexagon/cpu.c | 3 + target/hexagon/mmvec/hvx_ieee_fp.c | 69 +++++++++++++++ target/hexagon/hex_common.py | 1 + target/hexagon/imported/mmvec/encode_ext.def | 18 ++++ target/hexagon/imported/mmvec/ext.idef | 93 ++++++++++++++++++++ target/hexagon/meson.build | 1 + 12 files changed, 248 insertions(+) create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.h create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.c diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index d28beaa92f..5a008d1949 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -87,6 +87,7 @@ typedef struct CPUArchState { MemLog mem_log_stores[STORES_MAX]; =20 float_status fp_status; + float_status hvx_fp_status; =20 target_ulong llsc_addr; target_ulong llsc_val; diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h new file mode 100644 index 0000000000..5577179abd --- /dev/null +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_HVX_IEEE_H +#define HEXAGON_HVX_IEEE_H + +#include "fpu/softfloat.h" + +/* Hexagon canonical NaN */ +#define FP32_DEF_NAN 0x7FFFFFFF +#define FP16_DEF_NAN 0x7FFF + +/* + * IEEE - FP ADD/SUB/MPY instructions + */ +uint32_t fp_mult_sf_sf(uint32_t a1, uint32_t a2, float_status *fp_status); +uint32_t fp_add_sf_sf(uint32_t a1, uint32_t a2, float_status *fp_status); +uint32_t fp_sub_sf_sf(uint32_t a1, uint32_t a2, float_status *fp_status); + +uint16_t fp_mult_hf_hf(uint16_t a1, uint16_t a2, float_status *fp_status); +uint16_t fp_add_hf_hf(uint16_t a1, uint16_t a2, float_status *fp_status); +uint16_t fp_sub_hf_hf(uint16_t a1, uint16_t a2, float_status *fp_status); + +uint32_t fp_mult_sf_hf(uint16_t a1, uint16_t a2, float_status *fp_status); +uint32_t fp_add_sf_hf(uint16_t a1, uint16_t a2, float_status *fp_status); +uint32_t fp_sub_sf_hf(uint16_t a1, uint16_t a2, float_status *fp_status); + +/* + * IEEE - FP Accumulate instructions + */ +uint16_t fp_mult_hf_hf_acc(uint16_t a1, uint16_t a2, uint16_t acc, + float_status *fp_status); +uint32_t fp_mult_sf_hf_acc(uint16_t a1, uint16_t a2, uint32_t acc, + float_status *fp_status); + +/* + * IEEE - FP Reduce instructions + */ +uint32_t fp_vdmpy(uint16_t a1, uint16_t a2, uint16_t a3, uint16_t a4, + float_status *fp_status); +uint32_t fp_vdmpy_acc(uint32_t acc, uint16_t a1, uint16_t a2, uint16_t a3, + uint16_t a4, float_status *fp_status); + +#endif diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index c7840fbf2e..ac709d8993 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -23,6 +23,7 @@ #include "mmvec/system_ext_mmvec.h" #include "accel/tcg/getpc.h" #include "accel/tcg/probe.h" +#include "mmvec/hvx_ieee_fp.h" =20 #ifndef QEMU_GENERATE #define VdV (*(MMVector *restrict)(VdV_void)) diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index 52d470709c..eaedfe0d6d 100644 --- a/target/hexagon/mmvec/mmvec.h +++ b/target/hexagon/mmvec/mmvec.h @@ -38,6 +38,8 @@ typedef union { int16_t h[MAX_VEC_SIZE_BYTES / 2]; uint8_t ub[MAX_VEC_SIZE_BYTES / 1]; int8_t b[MAX_VEC_SIZE_BYTES / 1]; + int32_t sf[MAX_VEC_SIZE_BYTES / 4]; /* single float (32-bit) */ + int16_t hf[MAX_VEC_SIZE_BYTES / 2]; /* half float (16-bit) */ } MMVector; =20 typedef union { diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index c85cd5d17c..d3c4bf6301 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -175,6 +175,10 @@ DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be us= ed as a .new.", "", "") =20 /* HVX IEEE FP extension attributes */ DEF_ATTRIB(HVX_IEEE_FP, "HVX IEEE FP extension instruction", "", "") +DEF_ATTRIB(HVX_IEEE_FP_ACC, "HVX IEEE FP accumulate instruction", "", "") +DEF_ATTRIB(HVX_IEEE_FP_OUT_16, "HVX IEEE FP 16-bit output", "", "") +DEF_ATTRIB(HVX_IEEE_FP_OUT_32, "HVX IEEE FP 32-bit output", "", "") +DEF_ATTRIB(CVI_VX_NO_TMP_LD, "HVX multiply without tmp load", "", "") =20 /* Keep this as the last attribute: */ DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index e17e714a6a..358aa71e03 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -199,6 +199,10 @@ void arch_fpop_start(CPUHexagonState *env) set_float_rounding_mode( softfloat_roundingmodes[fREAD_REG_FIELD(USR, USR_FPRND)], &env->fp_status); + /* + * No need to check env->hvx_fp_status, these instructions don't + * raise exceptions nor interact with usr fields. + */ } =20 #ifdef CONFIG_USER_ONLY @@ -232,6 +236,10 @@ void arch_fpop_end(CPUHexagonState *env, bool pkt_need= _commit) SOFTFLOAT_TEST_FLAG(float_flag_overflow, FPOVFF, FPOVFE); SOFTFLOAT_TEST_FLAG(float_flag_underflow, FPUNFF, FPUNFE); } + /* + * No need to check env->hvx_fp_status, these instructions don't + * raise exceptions nor interact with usr fields. + */ } =20 int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjus= t, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index d7f4df5f96..d6ca51f175 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -300,6 +300,9 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) set_float_detect_tininess(float_tininess_before_rounding, &env->fp_sta= tus); /* Default NaN value: sign bit set, all frac bits set */ set_float_default_nan_pattern(0b11111111, &env->fp_status); + + set_default_nan_mode(1, &env->hvx_fp_status); + set_float_default_nan_pattern(0b01111111, &env->hvx_fp_status); } =20 static void hexagon_cpu_disas_set_info(const CPUState *cs, diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c new file mode 100644 index 0000000000..ceb32ce43b --- /dev/null +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hvx_ieee_fp.h" + +#define DEF_FP_INSN_2(name, rt, a1t, a2t, op) \ + uint##rt##_t fp_##name(uint##a1t##_t a1, uint##a2t##_t a2, \ + float_status *fp_status) { \ + float##a1t f1 =3D make_float##a1t(a1); \ + float##a2t f2 =3D make_float##a2t(a2); \ + return (op); \ + } + +#define DEF_FP_INSN_3(name, rt, a1t, a2t, a3t, op) \ + uint##rt##_t fp_##name(uint##a1t##_t a1, uint##a2t##_t a2, \ + uint##a3t##_t a3, float_status *fp_status) { \ + float##a1t f1 =3D make_float##a1t(a1); \ + float##a2t f2 =3D make_float##a2t(a2); \ + float##a3t f3 =3D make_float##a3t(a3); \ + return (op); \ + } + +DEF_FP_INSN_2(mult_sf_sf, 32, 32, 32, float32_mul(f1, f2, fp_status)) +DEF_FP_INSN_2(add_sf_sf, 32, 32, 32, float32_add(f1, f2, fp_status)) +DEF_FP_INSN_2(sub_sf_sf, 32, 32, 32, float32_sub(f1, f2, fp_status)) + +DEF_FP_INSN_2(mult_hf_hf, 16, 16, 16, float16_mul(f1, f2, fp_status)) +DEF_FP_INSN_2(add_hf_hf, 16, 16, 16, float16_add(f1, f2, fp_status)) +DEF_FP_INSN_2(sub_hf_hf, 16, 16, 16, float16_sub(f1, f2, fp_status)) + +DEF_FP_INSN_2(mult_sf_hf, 32, 16, 16, + float32_mul(float16_to_float32(f1, true, fp_status), + float16_to_float32(f2, true, fp_status), + fp_status)) +DEF_FP_INSN_2(add_sf_hf, 32, 16, 16, + float32_add(float16_to_float32(f1, true, fp_status), + float16_to_float32(f2, true, fp_status), + fp_status)) +DEF_FP_INSN_2(sub_sf_hf, 32, 16, 16, + float32_sub(float16_to_float32(f1, true, fp_status), + float16_to_float32(f2, true, fp_status), + fp_status)) + +DEF_FP_INSN_3(mult_hf_hf_acc, 16, 16, 16, 16, + float16_muladd(f1, f2, f3, 0, fp_status)) +DEF_FP_INSN_3(mult_sf_hf_acc, 32, 16, 16, 32, + float32_muladd(float16_to_float32(f1, true, fp_status), + float16_to_float32(f2, true, fp_status), + f3, 0, fp_status)) + +uint32_t fp_vdmpy(uint16_t a1, uint16_t a2, uint16_t a3, uint16_t a4, + float_status *fp_status) +{ + float32 prod1 =3D fp_mult_sf_hf(a1, a3, fp_status); + float32 prod2 =3D fp_mult_sf_hf(a2, a4, fp_status); + return fp_add_sf_sf(float32_val(prod1), float32_val(prod2), fp_status); +} + +uint32_t fp_vdmpy_acc(uint32_t acc, uint16_t a1, uint16_t a2, + uint16_t a3, uint16_t a4, + float_status *fp_status) +{ + float32 red =3D fp_vdmpy(a1, a2, a3, a4, fp_status); + return fp_add_sf_sf(float32_val(red), acc, fp_status); +} diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 32a61505ce..9e8bcfdcf0 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -215,6 +215,7 @@ def need_env(tag): "A_LOAD" in attribdict[tag] or "A_CVI_GATHER" in attribdict[tag] or "A_CVI_SCATTER" in attribdict[tag] or + "A_HVX_IEEE_FP" in attribdict[tag] or "A_IMPLICIT_WRITES_USR" in attribdict[tag]) =20 =20 diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 6d70086b5f..4ce87d09fd 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -804,5 +804,23 @@ DEF_ENC(V6_vmpyewuh, ICLASS_CJ" 1 111 111 vvvvv PP = 0 uuuuu 101 ddddd") DEF_ENC(V6_vmpyowh, ICLASS_CJ" 1 111 111 vvvvv PP 0 uuuuu 111 ddddd= ") DEF_ENC(V6_vmpyuhvs,"00011111110vvvvvPP1uuuuu111ddddd") =20 +/* IEEE FP multiply instructions */ +DEF_ENC(V6_vmpy_sf_sf,"00011111100vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vmpy_sf_hf,"00011111100vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vmpy_hf_hf,"00011111100vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vdmpy_sf_hf,"00011111101vvvvvPP1uuuuu110ddddd") + +/* IEEE FP multiply-accumulate instructions */ +DEF_ENC(V6_vmpy_sf_hf_acc,"00011100010vvvvvPP1uuuuu001xxxxx") +DEF_ENC(V6_vmpy_hf_hf_acc,"00011100010vvvvvPP1uuuuu010xxxxx") +DEF_ENC(V6_vdmpy_sf_hf_acc,"00011100010vvvvvPP1uuuuu011xxxxx") + +/* IEEE FP add/sub instructions */ +DEF_ENC(V6_vadd_sf_sf,"00011111100vvvvvPP1uuuuu110ddddd") +DEF_ENC(V6_vsub_sf_sf,"00011111100vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vadd_sf_hf,"00011111100vvvvvPP1uuuuu100ddddd") +DEF_ENC(V6_vsub_sf_hf,"00011111100vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vadd_hf_hf,"00011111101vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vsub_hf_hf,"00011111011vvvvvPP1uuuuu000ddddd") =20 #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 03d31f6181..e800cda317 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -2895,9 +2895,102 @@ EXTINSN(V6_vprefixqw,"Vd32.w=3Dprefixsum(Qv4)", A= TTRIBS(A_EXTENSION,A_CVI,A_CVI_ } } ) =20 +/* KVX - IEEE FP Instructions */ =20 +/* Single pipe, 32-bit output */ +#define ITERATOR_INSN_IEEE_FP_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_32), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 +/* Single pipe, 16-bit output */ +#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 +/* Two pipes: P2 & P3, single output: P2, 32-bit output */ +#define ITERATOR_INSN_IEEE_FP_DOUBLE_SINGLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE= ) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32),= \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* Two pipes: P2 & P3, two outputs, 32-bit output */ +#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32),= \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* + * single pipe, accumulate instruction, produces 16-bit output, requires 1= 6-bit + * accumulate input + */ +#define ITERATOR_INSN_IEEE_FP_ACC_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_ACC,A_HVX_I= EEE_FP_OUT_16,A_CVI_VX_NO_TMP_LD), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* + * single pipe, accumulate instruction, produces 32-bit output, requires 3= 2-bit + * accumulate input + */ +#define ITERATOR_INSN_IEEE_FP_ACC_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ +ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_ACC,A_HVX_I= EEE_FP_OUT_32,A_CVI_VX_NO_TMP_LD), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* IEEE FP multiply instructions */ +ITERATOR_INSN_IEEE_FP_DOUBLE_SINGLE_32(32, vmpy_sf_sf, + "Vd32.sf=3Dvmpy(Vu32.sf,Vv32.sf)", "Vector IEEE mul: sf", + VdV.sf[i] =3D fp_mult_sf_sf(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_hf, + "Vdd32.sf=3Dvmpy(Vu32.hf,Vv32.hf)", "Vector IEEE mul: hf widen to sf", + VddV.v[0].sf[i] =3D fp_mult_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_= fp_status); + VddV.v[1].sf[i] =3D fp_mult_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->= hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16(16, vmpy_hf_hf, "Vd32.hf=3Dvmpy(Vu32.hf,Vv32.= hf)", + "Vector IEEE mul: hf", + VdV.hf[i] =3D fp_mult_hf_hf(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_32(32, vdmpy_sf_hf, "Vd32.sf=3Dvdmpy(Vu32.hf,Vv3= 2.hf)", + "Vector IEEE mul reduction: hf widen to sf", + VdV.sf[i] =3D fp_vdmpy(VuV.hf[2*i+1], VuV.hf[2*i], VvV.hf[2*i+1], + VvV.hf[2*i], &env->hvx_fp_status)) + +/* IEEE FP multiply-accumulate instructions */ +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_hf_acc, + "Vxx32.sf+=3Dvmpy(Vu32.hf,Vv32.hf)", "Vector IEEE fma: hf widen to sf", + VxxV.v[0].sf[i] =3D fp_mult_sf_hf_acc(VuV.hf[2*i], VvV.hf[2*i], + VxxV.v[0].sf[i], &env->hvx_fp_status); + VxxV.v[1].sf[i] =3D fp_mult_sf_hf_acc(VuV.hf[2*i+1], VvV.hf[2*i+1], + VxxV.v[1].sf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_ACC_16(16, vmpy_hf_hf_acc, + "Vx32.hf+=3Dvmpy(Vu32.hf,Vv32.hf)", "Vector IEEE fma: hf", + VxV.hf[i] =3D fp_mult_hf_hf_acc(VuV.hf[i], VvV.hf[i], VxV.hf[i], &env-= >hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_ACC_32(32, vdmpy_sf_hf_acc, + "Vx32.sf+=3Dvdmpy(Vu32.hf,Vv32.hf)", "Vector IEEE fma reduce: hf widen= to sf", + VxV.sf[i] =3D fp_vdmpy_acc(VxV.sf[i], VuV.hf[2*i+1], VuV.hf[2*i], VvV.= hf[2*i+1], + VvV.hf[2*i], &env->hvx_fp_status)) + +/* IEEE FP add/sub instructions */ +ITERATOR_INSN_IEEE_FP_32(32, vadd_sf_sf, "Vd32.sf=3Dvadd(Vu32.sf,Vv32.sf)", + "Vector IEEE add: sf", + VdV.sf[i] =3D fp_add_sf_sf(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_32(32, vsub_sf_sf, "Vd32.sf=3Dvsub(Vu32.sf,Vv32.sf)", + "Vector IEEE sub: sf", + VdV.sf[i] =3D fp_sub_sf_sf(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16(16, vadd_hf_hf, "Vd32.hf=3Dvadd(Vu32.hf,Vv32.hf)", + "Vector IEEE add: hf", + VdV.hf[i] =3D fp_add_hf_hf(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16(16, vsub_hf_hf, "Vd32.hf=3Dvsub(Vu32.hf,Vv32.hf)", + "Vector IEEE sub: hf", + VdV.hf[i] =3D fp_sub_hf_hf(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vadd_sf_hf, + "Vdd32.sf=3Dvadd(Vu32.hf,Vv32.hf)", "Vector IEEE add: hf widen to sf", + VddV.v[0].sf[i] =3D fp_add_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_f= p_status); + VddV.v[1].sf[i] =3D fp_add_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->h= vx_fp_status)) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf, + "Vdd32.sf=3Dvsub(Vu32.hf,Vv32.hf)", "Vector IEEE sub: hf widen to sf", + VddV.v[0].sf[i] =3D fp_sub_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_f= p_status); + VddV.v[1].sf[i] =3D fp_sub_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->h= vx_fp_status)) =20 /*************************************************************************= ***** DEBUG Vector/Register Printing diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index d169cf71b2..9195014821 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -250,6 +250,7 @@ hexagon_ss.add(files( 'fma_emu.c', 'mmvec/decode_ext_mmvec.c', 'mmvec/system_ext_mmvec.c', + 'mmvec/hvx_ieee_fp.c', )) =20 # --=20 2.37.2