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Sun, 24 Nov 2019 12:05:29 -0800 (PST) Received: from pontoon.com (unknown [17.234.36.164]) by nwk-mmpp-sz10.apple.com (Oracle Communications Messaging Server 8.0.2.4.20190507 64bit (built May 7 2019)) with ESMTPSA id <0Q1H000C0P54NN30@nwk-mmpp-sz10.apple.com>; Sun, 24 Nov 2019 12:05:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apple.com; h=sender : from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=20180706; bh=631i+E5+V3w/tMPntS6QFcgMcTtYiV0pvlXBW1bjmXA=; b=KDaSo0RPLNUQS0XWgd8vgsUdUP02HM3xTytFabX0FB5Cep2bY7vSVK8a2nG8kyKWmhb3 PJX5/NfsSfuDiq9/3rndu0lpo1sveEOaivr4QkDttF1MLS5w3TDPQoW0JWvFZj/AA8vm asSTcIb7aDJ4/5QO+VVdF5hqp1eoImfSWexR0CmhF4ufsjOptErsvlgydk2cpKxwihCE 9Mo3URa89s/nvjvTqqr6Y+w0vyNR/pLZOja2WY0t+BWUcsTs+3GjvOTeepGEpaCXenON BBxyfONNLwT6r83jXDTP2FnMw1XSLdJ79cWNqAAEP2W/vg8A5UKY+Dzt6x8jlgbNdFIM vQ== X-Va-A: X-Va-T-CD: c56cc4374afe9162bf6a337f3d661529 X-Va-E-CD: 9dc0bdaa47fefc899b9535aa263da81f X-Va-R-CD: adefe9b51cd7c25a3de7c46b7195bdc9 X-Va-CD: 0 X-Va-ID: 77f77e58-038c-47bc-84c1-0d3830f85798 X-V-A: X-V-T-CD: c56cc4374afe9162bf6a337f3d661529 X-V-E-CD: 9dc0bdaa47fefc899b9535aa263da81f X-V-R-CD: adefe9b51cd7c25a3de7c46b7195bdc9 X-V-CD: 0 X-V-ID: 1e954263-8d8e-4469-a389-5694a37c6fa3 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-11-24_02:,, signatures=0 To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 2/5] hvf: remove TSC synchronization code because it isn't fully complete Date: Sun, 24 Nov 2019 12:05:24 -0800 Message-id: <44c4afd2301b8bf99682b229b0796d84edd6d66f.1574625592.git.dirty@apple.com> X-Mailer: git-send-email 2.24.0 In-reply-to: References: MIME-version: 1.0 Content-transfer-encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-11-24_02:, , signatures=0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 17.171.2.60 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Cameron Esfahani From: Cameron Esfahani via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The existing code in QEMU's HVF support to attempt to synchronize TSC across multiple cores is not sufficient. TSC value on other cores can go backwards. Until implementation is fixed, remove calls to hv_vm_sync_tsc(). Pass through TSC to guest OS. Signed-off-by: Cameron Esfahani --- target/i386/hvf/hvf.c | 3 +-- target/i386/hvf/x86_emu.c | 3 --- target/i386/hvf/x86hvf.c | 4 ---- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 0b50cfcbc6..90fd50acfc 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -518,7 +518,6 @@ void hvf_reset_vcpu(CPUState *cpu) { wreg(cpu->hvf_fd, HV_X86_R8 + i, 0x0); } =20 - hv_vm_sync_tsc(0); hv_vcpu_invalidate_tlb(cpu->hvf_fd); hv_vcpu_flush(cpu->hvf_fd); } @@ -612,7 +611,7 @@ int hvf_init_vcpu(CPUState *cpu) hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1); - /*hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);*/ + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 1b04bd7e94..3df767209d 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -772,9 +772,6 @@ void simulate_wrmsr(struct CPUState *cpu) =20 switch (msr) { case MSR_IA32_TSC: - /* if (!osx_is_sierra()) - wvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET, data - rdtscp()); - hv_vm_sync_tsc(data);*/ break; case MSR_IA32_APICBASE: cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index e0ea02d631..1485b95776 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -152,10 +152,6 @@ void hvf_put_msrs(CPUState *cpu_state) =20 hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base); hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base); - - /* if (!osx_is_sierra()) - wvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET, env->tsc - rdtscp());*/ - hv_vm_sync_tsc(env->tsc); } =20 =20 --=20 2.24.0