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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=612374860=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/sifive_u.c | 55 ++++++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d550befadb..7216329237 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -60,12 +60,6 @@ =20 #include =20 -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -93,7 +87,7 @@ static const struct MemmapEntry { #define GEM_REVISION 0x10070109 =20 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_= bit) { MachineState *ms =3D MACHINE(qdev_get_machine()); void *fdt; @@ -178,11 +172,11 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, qemu_fdt_add_subnode(fdt, nodename); /* cpu 0 is the management hart that does not have mmu */ if (cpu !=3D 0) { -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32= "); -#else - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48= "); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,= sv32"); + } else { + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,= sv48"); + } isa =3D riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); } else { isa =3D riscv_isa_string(&s->soc.e_cpus.harts[0]); @@ -458,7 +452,8 @@ static void sifive_u_machine_init(MachineState *machine) qemu_allocate_irq(sifive_u_machine_reset, NULL, = 0)); =20 /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32_bit(machine)); =20 if (s->start_in_flash) { /* @@ -487,8 +482,15 @@ static void sifive_u_machine_init(MachineState *machin= e) break; } =20 - firmware_end_addr =3D riscv_find_and_load_firmware(machine, BIOS_FILEN= AME, - start_addr, NULL); + if (riscv_is_32_bit(machine)) { + firmware_end_addr =3D riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.bi= n", + start_addr, NULL); + } else { + firmware_end_addr =3D riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.bi= n", + start_addr, NULL); + } =20 if (machine->kernel_filename) { kernel_start_addr =3D riscv_calc_kernel_start_addr(machine, @@ -518,9 +520,9 @@ static void sifive_u_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, machine->ram_size, s->fdt); - #if defined(TARGET_RISCV64) - start_addr_hi32 =3D start_addr >> 32; - #endif + if (!riscv_is_32_bit(machine)) { + start_addr_hi32 =3D (uint64_t)start_addr >> 32; + } =20 /* reset vector */ uint32_t reset_vec[11] =3D { @@ -528,13 +530,8 @@ static void sifive_u_machine_init(MachineState *machin= e) 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn)= */ 0x02828613, /* addi a2, t0, %pcrel_lo(1b)= */ 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0202a583, /* lw a1, 32(t0) */ - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0202b583, /* ld a1, 32(t0) */ - 0x0182b283, /* ld t0, 24(t0) */ -#endif + 0, + 0, 0x00028067, /* jr t0 */ start_addr, /* start: .dword */ start_addr_hi32, @@ -542,6 +539,14 @@ static void sifive_u_machine_init(MachineState *machin= e) 0x00000000, /* fw_dyn: */ }; + if (riscv_is_32_bit(machine)) { + reset_vec[4] =3D 0x0202a583; /* lw a1, 32(t0) */ + reset_vec[5] =3D 0x0182a283; /* lw t0, 24(t0) */ + } else { + reset_vec[4] =3D 0x0202b583; /* ld a1, 32(t0) */ + reset_vec[5] =3D 0x0182b283; /* ld t0, 24(t0) */ + } + =20 /* copy in the reset vector in little_endian byte order */ for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { --=20 2.29.2