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x=1614821786; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dpSnUXJsfXsvbPky0lT+EZH/OqTvD/6BTmdDhhB8700=; b=EK+o82aa0jdZaagNLcFMUoe6NJCP9bVyw+L+rvXWv2G/rzottXk0NULJ kPuzCc3WOXF8Jo78aT8yhlmccv8jVzLhXELZhMv+HRFXhnF0R5VYMUhqQ fwLnqPfyztRKOTWVLNXul5itYw1CQDPDEJRbF6RNuqeItXmJMnLD3eJsP 15uEHl5+0w0cA4AaDcrXkKhFK69ThQs3ODZodYgj04PIgr9N5C0XWHbxD Qts1cTR1okShrY8YTW4BO5Nx3tztrvI4mZOXcXnqLhZrED7iNNS9RLeZ+ I0lHpSzJAowobB2nf22KpFJPAyU0lC4WA6VINzBuqZqPrCSYd4K6jk+EH Q==; IronPort-SDR: Nio2yPUxEPcBGTKlum4bit4OoaZ6CusA4LlWyT/m3uUfh3BMG1LHcb+KYIWuaAdJcinY0KiLbo nLUv0K7C0t+B1FSftl36Ztj4wPywIjiOma3PX4NNBPxSElgAfSZruP26tLA3IgjJyfM2vq5Ufr WjAcN0JreUYaVE1UWBJfFAVH++d0yVnLGTZnNgYcz6ATOww2BGE71CKYMkrXOPY2JhGIt/gMrh V11yBAB8INcPUOOx2MDZxhrmTYzFwpadgY1/yGYmaqxZmZ84FrPryDAN6o8wtj4rRpUrN/1c/2 tCI= X-IronPort-AV: E=Sophos;i="5.70,511,1574092800"; d="scan'208";a="131866039" IronPort-SDR: 7Fc3Fiwxm3f8Hgybe5fBXiaM3Kz+UDKS090Gw+yzW1WyIW+pH1H9jfcjrzq3IhnYlfEmaIn6IS 1bYSE76uBQwtfujKGyCw3o4tO3sgWCTEAIH1A66zRwDiV1Tv+wyIpIyEAujZsa3MtsTDo23AAa uWBlrH97w80M5uLYZTuSDNlo2JemXG+gRw/OoudHKW0c28vMltx9CaZFwr1Nt0SsF3kEiUmnRG MFX2JwLISwsFAqpMKf8OeSWRO2PtGBL4PVsBWYJIf1BK4y0/ol5/ctAsjnyJYILtFl8yaZPjR9 Yb9hEUJq5OMRtERYS3mxNBdX IronPort-SDR: TS3hUjm8PVfy/0cd5gx1UeyGkD9BLkXojD54vlPz3T0EDj7wWjZxCHRMXcHvocGtywyAU7M2S3 8DbsvLB8fcOhbh/6qYK+b2wQ5RXjxUxwndp7ABGQmnXXUka0UYLlObelTW/3V0Og//xRNpY/0g Nd6edrF8/4d52kC5XjHH5il997kYDaaJPxIBKVplN/5v6Nvp4u+BqILkw+vtNMM8RrO6KBWupF AQJ5m6sYQZcxK+zq/gGCoPjebsXXfMscaGpsaQzsUg9vlmNZ856VYi4t2sR+QZkf2HRRDW6mTH EgA= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 1/3] riscv/sifive_u: Fix up file ordering Date: Tue, 3 Mar 2020 17:29:10 -0800 Message-Id: <3f5f5106d357f6ff911e4b81973840d414920b78.1583285287.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.144 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Split the file into clear machine and SoC sections. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 107 ++++++++++++++++++++++---------------------- 1 file changed, 54 insertions(+), 53 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 156a003642..9a0145b5b4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -399,6 +399,60 @@ static void riscv_sifive_u_init(MachineState *machine) &address_space_memory); } =20 +static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **e= rrp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D value; +} + +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D false; + object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_= flash, + sifive_u_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to = " \ + "flash. Otherwise QEMU will jump to DR= AM", + NULL); +} + + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; + mc->init =3D riscv_sifive_u_init; + mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; + mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus =3D mc->min_cpus; +} + +static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sifive_u"), + .parent =3D TYPE_MACHINE, + .class_init =3D riscv_sifive_u_machine_class_init, + .instance_init =3D riscv_sifive_u_machine_instance_init, + .instance_size =3D sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) + static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -439,33 +493,6 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } =20 -static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - return s->start_in_flash; -} - -static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **e= rrp) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - s->start_in_flash =3D value; -} - -static void riscv_sifive_u_machine_instance_init(Object *obj) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - s->start_in_flash =3D false; - object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_= flash, - sifive_u_set_start_in_flash, NULL); - object_property_set_description(obj, "start-in-flash", - "Set on to tell QEMU's ROM to jump to = " \ - "flash. Otherwise QEMU will jump to DR= AM", - NULL); -} - static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -603,29 +630,3 @@ static void riscv_sifive_u_soc_register_types(void) } =20 type_init(riscv_sifive_u_soc_register_types) - -static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - - mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; - mc->init =3D riscv_sifive_u_init; - mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; - mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus =3D mc->min_cpus; -} - -static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { - .name =3D MACHINE_TYPE_NAME("sifive_u"), - .parent =3D TYPE_MACHINE, - .class_init =3D riscv_sifive_u_machine_class_init, - .instance_init =3D riscv_sifive_u_machine_instance_init, - .instance_size =3D sizeof(SiFiveUState), -}; - -static void riscv_sifive_u_machine_init_register_types(void) -{ - type_register_static(&riscv_sifive_u_machine_typeinfo); -} - -type_init(riscv_sifive_u_machine_init_register_types) --=20 2.25.1