From nobody Mon Feb 9 08:33:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660406146724876.6064814416937; Sat, 13 Aug 2022 08:55:46 -0700 (PDT) Received: from localhost ([::1]:45730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtUH-0007Au-KQ for importer@patchew.org; Sat, 13 Aug 2022 11:55:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9v-0000PE-A4; Sat, 13 Aug 2022 11:34:43 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9t-0006Ko-7I; Sat, 13 Aug 2022 11:34:43 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id BFD87748194; Sat, 13 Aug 2022 17:34:39 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 8ED1574818E; Sat, 13 Aug 2022 17:34:39 +0200 (CEST) Message-Id: <3f182ba0e89eeea855516cf3651fb8cc4cf9b546.1660402839.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 12/22] ppc4xx: Move PLB model to ppc4xx_devs.c MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:39 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660406148051100001 Content-Type: text/plain; charset="utf-8" The PLB is shared between 405 and 440 so move it to the shared file. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 11 ----- hw/ppc/ppc405_uc.c | 93 ---------------------------------------- hw/ppc/ppc4xx_devs.c | 94 +++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/ppc4xx.h | 11 +++++ 4 files changed, 105 insertions(+), 104 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 31c94e4742..d85c595f9d 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,17 +63,6 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 -/* Peripheral local bus arbitrer */ -#define TYPE_PPC405_PLB "ppc405-plb" -OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB); -struct Ppc405PlbState { - Ppc4xxDcrDeviceState parent_obj; - - uint32_t acr; - uint32_t bear; - uint32_t besr; -}; - /* PLB to OPB bridge */ #define TYPE_PPC405_POB "ppc405-pob" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 922c23346f..3de6c77631 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -137,94 +137,6 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_a= ddr_t ram_size) /*************************************************************************= ****/ /* Shared peripherals */ =20 -/*************************************************************************= ****/ -/* Peripheral local bus arbitrer */ -enum { - PLB3A0_ACR =3D 0x077, - PLB4A0_ACR =3D 0x081, - PLB0_BESR =3D 0x084, - PLB0_BEAR =3D 0x086, - PLB0_ACR =3D 0x087, - PLB4A1_ACR =3D 0x089, -}; - -static uint32_t dcr_read_plb(void *opaque, int dcrn) -{ - Ppc405PlbState *plb =3D opaque; - uint32_t ret; - - switch (dcrn) { - case PLB0_ACR: - ret =3D plb->acr; - break; - case PLB0_BEAR: - ret =3D plb->bear; - break; - case PLB0_BESR: - ret =3D plb->besr; - break; - default: - /* Avoid gcc warning */ - ret =3D 0; - break; - } - - return ret; -} - -static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) -{ - Ppc405PlbState *plb =3D opaque; - - switch (dcrn) { - case PLB0_ACR: - /* We don't care about the actual parameters written as - * we don't manage any priorities on the bus - */ - plb->acr =3D val & 0xF8000000; - break; - case PLB0_BEAR: - /* Read only */ - break; - case PLB0_BESR: - /* Write-clear */ - plb->besr &=3D ~val; - break; - } -} - -static void ppc405_plb_reset(DeviceState *dev) -{ - Ppc405PlbState *plb =3D PPC405_PLB(dev); - - plb->acr =3D 0x00000000; - plb->bear =3D 0x00000000; - plb->besr =3D 0x00000000; -} - -static void ppc405_plb_realize(DeviceState *dev, Error **errp) -{ - Ppc405PlbState *plb =3D PPC405_PLB(dev); - Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); - - ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); - ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); - ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); - ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb= ); - ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb= ); - ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); -} - -static void ppc405_plb_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - - dc->realize =3D ppc405_plb_realize; - dc->reset =3D ppc405_plb_reset; - /* Reason: only works as function of a ppc4xx SoC */ - dc->user_creatable =3D false; -} - /*************************************************************************= ****/ /* PLB to OPB bridge */ enum { @@ -1535,11 +1447,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { - .name =3D TYPE_PPC405_PLB, - .parent =3D TYPE_PPC4xx_DCR_DEVICE, - .instance_size =3D sizeof(Ppc405PlbState), - .class_init =3D ppc405_plb_class_init, - }, { .name =3D TYPE_PPC405_POB, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405PobState), diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 7d40c1b68a..843d759b1b 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -658,6 +658,95 @@ static void ppc4xx_mal_class_init(ObjectClass *oc, voi= d *data) device_class_set_props(dc, ppc4xx_mal_properties); } =20 +/*************************************************************************= ****/ +/* Peripheral local bus arbitrer */ +enum { + PLB3A0_ACR =3D 0x077, + PLB4A0_ACR =3D 0x081, + PLB0_BESR =3D 0x084, + PLB0_BEAR =3D 0x086, + PLB0_ACR =3D 0x087, + PLB4A1_ACR =3D 0x089, +}; + +static uint32_t dcr_read_plb(void *opaque, int dcrn) +{ + Ppc405PlbState *plb =3D opaque; + uint32_t ret; + + switch (dcrn) { + case PLB0_ACR: + ret =3D plb->acr; + break; + case PLB0_BEAR: + ret =3D plb->bear; + break; + case PLB0_BESR: + ret =3D plb->besr; + break; + default: + /* Avoid gcc warning */ + ret =3D 0; + break; + } + + return ret; +} + +static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) +{ + Ppc405PlbState *plb =3D opaque; + + switch (dcrn) { + case PLB0_ACR: + /* + * We don't care about the actual parameters written as + * we don't manage any priorities on the bus + */ + plb->acr =3D val & 0xF8000000; + break; + case PLB0_BEAR: + /* Read only */ + break; + case PLB0_BESR: + /* Write-clear */ + plb->besr &=3D ~val; + break; + } +} + +static void ppc405_plb_reset(DeviceState *dev) +{ + Ppc405PlbState *plb =3D PPC405_PLB(dev); + + plb->acr =3D 0x00000000; + plb->bear =3D 0x00000000; + plb->besr =3D 0x00000000; +} + +static void ppc405_plb_realize(DeviceState *dev, Error **errp) +{ + Ppc405PlbState *plb =3D PPC405_PLB(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); + ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); + ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); + ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb= ); + ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb= ); + ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_pl= b); +} + +static void ppc405_plb_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_plb_realize; + dc->reset =3D ppc405_plb_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; +} + /* PPC4xx_DCR_DEVICE */ =20 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, @@ -694,6 +783,11 @@ static const TypeInfo ppc4xx_types[] =3D { .instance_size =3D sizeof(Ppc4xxMalState), .instance_finalize =3D ppc4xx_mal_finalize, .class_init =3D ppc4xx_mal_class_init, + }, { + .name =3D TYPE_PPC405_PLB, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405PlbState), + .class_init =3D ppc405_plb_class_init, }, { .name =3D TYPE_PPC4xx_DCR_DEVICE, .parent =3D TYPE_SYS_BUS_DEVICE, diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index f40bd49bc7..e696e159f3 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -83,4 +83,15 @@ struct Ppc4xxMalState { uint8_t rxcnum; }; =20 +/* Peripheral local bus arbitrer */ +#define TYPE_PPC405_PLB "ppc405-plb" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB); +struct Ppc405PlbState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t acr; + uint32_t bear; + uint32_t besr; +}; + #endif /* PPC4XX_H */ --=20 2.30.4