From nobody Fri Dec 19 20:37:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1572047153; cv=none; d=zoho.com; s=zohoarc; b=GNsZIkWDJst7WPxklOyko70TXmqwdFDW5QRmZWadUwEADJkLXzvJoLoXXv2Ffc8l7ia0Lh+7YkA1Ba3lj5O1VUWOBrV5IuOkanYUSALFjEjzD0AuXlDXwjuBOODNWB9VaRD+GAapKAZ3dqSf1FEnn2VwInZWYg4iju68gXWY0Uc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572047153; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ox+mCnkexgz3q/0LOHjnJsTKipb6qoyedG+0CoMHdtI=; b=gsSe4CZe0rWItApuEmmByXRo4SMu70Iq3uCWrKt6NO2MT2wBF4Z9HQhcr/8Iw7rQv8cKgUdAAPzyD+y9HZ9ewVanh1WsbsNa30eezBIqRQ/N6zp6lf2zxgBoMKjuRt28Kgb4/ANQpVL6Od4wxaqQbZfFDy+HdpD37kr5pF/IVsw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1572047153273440.5074039406519; Fri, 25 Oct 2019 16:45:53 -0700 (PDT) Received: from localhost ([::1]:37102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO9HD-00029w-2W for importer@patchew.org; Fri, 25 Oct 2019 19:45:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49774) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO90z-00056D-UZ for qemu-devel@nongnu.org; Fri, 25 Oct 2019 19:29:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iO90v-0004KY-U7 for qemu-devel@nongnu.org; Fri, 25 Oct 2019 19:29:05 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:10433) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iO90s-0004DA-6f; Fri, 25 Oct 2019 19:28:59 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 26 Oct 2019 07:28:41 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2019 16:24:07 -0700 Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip01.wdc.com with ESMTP; 25 Oct 2019 16:28:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1572046138; x=1603582138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CTrr4qdivPfJC5uFIs0kK2KS6KzaJSQCgGtWYHEHsP8=; b=L878mvZl9Ru1ttD7s9xWi3eRTS0GC4SgsYiCT3PcopSVxhjYAgz+vQtN Ux+WZF0uPzx5c7/1/jNjFrt0ebck0MCj4cqLuG//WtjzDnkgNtO5SelRf zOFTEFU1cws1/NXD5hzdU0fIdzNEGlQ56ZMckN8WIqKYMIUlgFX4exAXu 62v4EmvNiEaLJBit4JVUeKmTEeTkFc3q0La4kK8GNDKo/FCXyDSSPqidH vrEfVrQ1PrVPbFYJx6Sj45MXMCi3FN4fFT59lwTYUuYN0xe2ecWUDNqgS P8dzwbn6fyI5dLS8ep68mannlvnzzN2zPvhQO3JogaTFcLp8z4H6WWl4C A==; IronPort-SDR: HemOfHT8dBG6LysUmGdTO/mQ5ph8rI7nsvMM6Tdojul7BAaTLDD2LMlYVqPbWzoFiE9nu5rh1k E4EuibP5K4omrv75v6gnKRcYdhGukaBHsv+lyRttUFpO8MwDnHYyRMy4xQzbvLYui5tSamVoPZ xXoNcKGct8/0mZ9EmhE19OHIIya+EHrIn+mdng/K4Y/ZZP9uxV+V/MRMQ5dZtl/Zc4qzbsXyh9 ibkold4qhY+bokRlsUF/U3loNlO2h/rMaRg3aX8NrTKBXB19ji3LtvHMEFGnnN4I66CV5CJuBg V3o= X-IronPort-AV: E=Sophos;i="5.68,230,1569254400"; d="scan'208";a="228520405" IronPort-SDR: bfnx9PCikoj75w8jTdDPON1FRg3hAUVJ6luQTBupmS/+SGmFgDFMvSOCwd8V8ZX1HGwzgLtMer J+Zma46Ht39ZESN4Y6QqGl6TkFEofv3IvvQpSVBpCxHYzORQ0PjFbpronpyBxv/Zg2blMum3ZW xjaXV6HK+itpz9mwk4RANbKDA1eBkeJhAy6WLaW1XpNeBdVqJ2qRZDtcVO6Ou+ax8cPpa6yf4/ TLJ2lbxU49uO/H5yoQqvbh/SSwsnfbLqigIDsYojcr7s+01b0bnpfUsOeie+4N+ONawbcAwapV banqU3iUEYJGwhJwq6h0bSYS IronPort-SDR: MVT5WQEUQwrB2J/NGEqhyo1i9GNVAd5R/c+2+8ua9esbsidsKkabsCjl+Otn3FRVEDWU4q/+xk m5EMv+SB1ENOHALc6ltwb+QCsKzkz5KWSx3VM6FNhCAxN1ECQ3MFqzc9uq0fjnYNR5QO21hN3x dKjHRBAK3ibjsiK26XOB2Wo2vEXzauu9EVhODkmRG7pkMBzZVJ8684q1fA4itxt+wv763bZjIl bnKWPpV2Xvixa+5RIPhuIFOeaqf69nHiG5yr8gii9/2dnDcMfhswa+jgzHOJyVwF1DLRow++6I /A8= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers Date: Fri, 25 Oct 2019 16:23:46 -0700 Message-Id: <3da1c9355946d5571787f9c87ff98a74061bed76.1572045716.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 68.232.141.245 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" To handle the new Hypervisor CSR register aliasing let's use pointers. We only need to convert the MIE and MSTATUS CSRs. With the exception of MIP all of the other CSRs that swap with virtulsation changes are S-Mode only, so we can just do a lazy switch. This because more challenging for the M-Mode registers so it ends up being easier to use pointers. As the MIP CSR is always accessed atomicly the pointer swap doesn't work so we leave that as is. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 16 ++++++++++++---- target/riscv/cpu.h | 12 ++++++++++-- target/riscv/cpu_helper.c | 32 ++++++++++++++++---------------- target/riscv/csr.c | 28 ++++++++++++++-------------- target/riscv/op_helper.c | 14 +++++++------- 5 files changed, 59 insertions(+), 43 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e66fd300fd..f75c709e35 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -228,7 +228,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", *env->mstatus); if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatu= s); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstatus ", env->vsstat= us); @@ -238,7 +238,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsip ", (target_ulong)atomic_read(&env->vsip)); } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", *env->mie); if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsie ", env->vsie); } @@ -308,7 +308,7 @@ static bool riscv_cpu_has_work(CPUState *cs) * Definition of the WFI instruction requires it to ignore the privile= ge * mode and delegation registers, but respect individual enables */ - return (env->mip & env->mie) !=3D 0; + return (env->mip & *env->mie) !=3D 0; #else return true; #endif @@ -329,7 +329,7 @@ static void riscv_cpu_reset(CPUState *cs) mcc->parent_reset(cs); #ifndef CONFIG_USER_ONLY env->priv =3D PRV_M; - env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); + *env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause =3D 0; env->pc =3D env->resetvec; #endif @@ -458,8 +458,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); +#ifndef CONFIG_USER_ONLY + CPURISCVState *env =3D &cpu->env; +#endif =20 cpu_set_cpustate_pointers(cpu); + +#ifndef CONFIG_USER_ONLY + env->mie =3D &env->mie_novirt; + env->mstatus =3D &env->mstatus_novirt; +#endif } =20 static const VMStateDescription vmstate_riscv_cpu =3D { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a1625e8af0..5b71ee416f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -122,12 +122,12 @@ struct CPURISCVState { target_ulong resetvec; =20 target_ulong mhartid; - target_ulong mstatus; + target_ulong *mstatus; =20 target_ulong mip; uint32_t miclaim; =20 - target_ulong mie; + target_ulong *mie; target_ulong mideleg; =20 target_ulong sptbr; /* until: priv-1.9.1 */ @@ -145,6 +145,14 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + /* The following registers are the "real" versions that the pointer + * versions point to. These should never be used unless you know what = you + * are doing. To access these use the pointer versions instead. This is + * required to handle the Hypervisor register swapping. + */ + target_ulong mie_novirt; + target_ulong mstatus_novirt; + /* Hypervisor CSRs */ target_ulong hstatus; target_ulong hedeleg; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1464f73bee..21d049cdce 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -37,9 +37,9 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { - target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); - target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); - target_ulong pending =3D env->mip & env->mie; + target_ulong mstatus_mie =3D get_field(*env->mstatus, MSTATUS_MIE); + target_ulong mstatus_sie =3D get_field(*env->mstatus, MSTATUS_SIE); + target_ulong pending =3D env->mip & *env->mie; target_ulong mie =3D env->priv < PRV_M || (env->priv =3D=3D PRV_M && m= status_mie); target_ulong sie =3D env->priv < PRV_S || (env->priv =3D=3D PRV_S && m= status_sie); target_ulong irqs =3D (pending & ~env->mideleg & -mie) | @@ -75,7 +75,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) /* Return true is floating point support is currently enabled */ bool riscv_cpu_fp_enabled(CPURISCVState *env) { - if (env->mstatus & MSTATUS_FS) { + if (*env->mstatus & MSTATUS_FS) { return true; } =20 @@ -198,8 +198,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, int mode =3D mmu_idx; =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); + if (get_field(*env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(*env->mstatus, MSTATUS_MPP); } } =20 @@ -213,11 +213,11 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 hwaddr base; int levels, ptidxbits, ptesize, vm, sum; - int mxr =3D get_field(env->mstatus, MSTATUS_MXR); + int mxr =3D get_field(*env->mstatus, MSTATUS_MXR); =20 if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; - sum =3D get_field(env->mstatus, MSTATUS_SUM); + sum =3D get_field(*env->mstatus, MSTATUS_SUM); vm =3D get_field(env->satp, SATP_MODE); switch (vm) { case VM_1_10_SV32: @@ -237,8 +237,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } } else { base =3D (hwaddr)(env->sptbr) << PGSHIFT; - sum =3D !get_field(env->mstatus, MSTATUS_PUM); - vm =3D get_field(env->mstatus, MSTATUS_VM); + sum =3D !get_field(*env->mstatus, MSTATUS_PUM); + vm =3D get_field(*env->mstatus, MSTATUS_VM); switch (vm) { case VM_1_09_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; @@ -493,8 +493,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx); =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); + if (get_field(*env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(*env->mstatus, MSTATUS_MPP); } } =20 @@ -607,12 +607,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (env->priv <=3D PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { /* handle the trap in S-mode */ - target_ulong s =3D env->mstatus; + target_ulong s =3D *env->mstatus; s =3D set_field(s, MSTATUS_SPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); - env->mstatus =3D s; + *env->mstatus =3D s; env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); env->sepc =3D env->pc; env->sbadaddr =3D tval; @@ -621,12 +621,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_mode(env, PRV_S); } else { /* handle the trap in M-mode */ - target_ulong s =3D env->mstatus; + target_ulong s =3D *env->mstatus; s =3D set_field(s, MSTATUS_MPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); - env->mstatus =3D s; + *env->mstatus =3D s; env->mcause =3D cause | ~(((target_ulong)-1) >> async); env->mepc =3D env->pc; env->mbadaddr =3D tval; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a1eb15f507..ef9c95f94d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -136,7 +136,7 @@ static int write_fflags(CPURISCVState *env, int csrno, = target_ulong val) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } - env->mstatus |=3D MSTATUS_FS; + *env->mstatus |=3D MSTATUS_FS; #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); return 0; @@ -159,7 +159,7 @@ static int write_frm(CPURISCVState *env, int csrno, tar= get_ulong val) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } - env->mstatus |=3D MSTATUS_FS; + *env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D val & (FSR_RD >> FSR_RD_SHIFT); return 0; @@ -183,7 +183,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } - env->mstatus |=3D MSTATUS_FS; + *env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); @@ -307,7 +307,7 @@ static int read_mhartid(CPURISCVState *env, int csrno, = target_ulong *val) /* Machine Trap Setup */ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mstatus; + *val =3D *env->mstatus; return 0; } =20 @@ -319,7 +319,7 @@ static int validate_vm(CPURISCVState *env, target_ulong= vm) =20 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong mstatus =3D env->mstatus; + target_ulong mstatus =3D *env->mstatus; target_ulong mask =3D 0; int dirty; =20 @@ -359,7 +359,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS)) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); - env->mstatus =3D mstatus; + *env->mstatus =3D mstatus; =20 return 0; } @@ -448,13 +448,13 @@ static int write_mideleg(CPURISCVState *env, int csrn= o, target_ulong val) =20 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mie; + *val =3D *env->mie; return 0; } =20 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) { - env->mie =3D (env->mie & ~all_ints) | (val & all_ints); + *env->mie =3D (*env->mie & ~all_ints) | (val & all_ints); return 0; } =20 @@ -608,7 +608,7 @@ static int read_sstatus(CPURISCVState *env, int csrno, = target_ulong *val) { target_ulong mask =3D ((env->priv_ver >=3D PRIV_VERSION_1_10_0) ? sstatus_v1_10_mask : sstatus_v1_9_mask); - *val =3D env->mstatus & mask; + *val =3D *env->mstatus & mask; return 0; } =20 @@ -616,19 +616,19 @@ static int write_sstatus(CPURISCVState *env, int csrn= o, target_ulong val) { target_ulong mask =3D ((env->priv_ver >=3D PRIV_VERSION_1_10_0) ? sstatus_v1_10_mask : sstatus_v1_9_mask); - target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); + target_ulong newval =3D (*env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } =20 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mie & env->mideleg; + *val =3D *env->mie & env->mideleg; return 0; } =20 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval =3D (env->mie & ~env->mideleg) | (val & env->midel= eg); + target_ulong newval =3D (*env->mie & ~env->mideleg) | (val & env->mide= leg); return write_mie(env, CSR_MIE, newval); } =20 @@ -731,7 +731,7 @@ static int read_satp(CPURISCVState *env, int csrno, tar= get_ulong *val) if (!riscv_feature(env, RISCV_FEATURE_MMU)) { *val =3D 0; } else if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { + if (env->priv =3D=3D PRV_S && get_field(*env->mstatus, MSTATUS_TVM= )) { return -1; } else { *val =3D env->satp; @@ -756,7 +756,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) validate_vm(env, get_field(val, SATP_MODE)) && ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { + if (env->priv =3D=3D PRV_S && get_field(*env->mstatus, MSTATUS_TVM= )) { return -1; } else { if((val ^ env->satp) & SATP_ASID) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 331cc36232..d150551bc9 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -83,11 +83,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) } =20 if (env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TSR)) { + get_field(*env->mstatus, MSTATUS_TSR)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - target_ulong mstatus =3D env->mstatus; + target_ulong mstatus =3D *env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_SPP); mstatus =3D set_field(mstatus, env->priv_ver >=3D PRIV_VERSION_1_10_0 ? @@ -96,7 +96,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong= cpu_pc_deb) mstatus =3D set_field(mstatus, MSTATUS_SPIE, 0); mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); - env->mstatus =3D mstatus; + *env->mstatus =3D mstatus; =20 return retpc; } @@ -112,7 +112,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - target_ulong mstatus =3D env->mstatus; + target_ulong mstatus =3D *env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); mstatus =3D set_field(mstatus, env->priv_ver >=3D PRIV_VERSION_1_10_0 ? @@ -121,7 +121,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) mstatus =3D set_field(mstatus, MSTATUS_MPIE, 0); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); - env->mstatus =3D mstatus; + *env->mstatus =3D mstatus; =20 return retpc; } @@ -132,7 +132,7 @@ void helper_wfi(CPURISCVState *env) =20 if (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TW)) { + get_field(*env->mstatus, MSTATUS_TW)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { cs->halted =3D 1; @@ -147,7 +147,7 @@ void helper_tlb_flush(CPURISCVState *env) if (!(env->priv >=3D PRV_S) || (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TVM))) { + get_field(*env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { tlb_flush(cs); --=20 2.23.0