From nobody Fri Nov 7 04:15:01 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546397882191653.6251103427064; Tue, 1 Jan 2019 18:58:02 -0800 (PST) Received: from localhost ([127.0.0.1]:41425 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1geWjI-00076N-OI for importer@patchew.org; Tue, 01 Jan 2019 21:58:00 -0500 Received: from eggs.gnu.org ([208.118.235.92]:35930) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1geWgV-0004PS-Ai for qemu-devel@nongnu.org; Tue, 01 Jan 2019 21:55:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1geWgT-0005SU-1k for qemu-devel@nongnu.org; Tue, 01 Jan 2019 21:55:07 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:60318) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1geWgS-0005Re-MZ; Tue, 01 Jan 2019 21:55:04 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 43A7E7456BC; Wed, 2 Jan 2019 03:54:43 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 9D56E7456C7; Wed, 2 Jan 2019 03:54:42 +0100 (CET) Message-Id: <3bba70dcccdf7a13aa961ed576fbf8ba88138dcf.1546394798.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 02 Jan 2019 03:06:38 +0100 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH 7/8] sam460ex: Fix support for memory larger than 1GB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix the encoding of larger memory modules in the SoC registers which allows specifying more than 1GB memory for sam460ex. Well, only 2GB due to SoC and firmware restrictions which was the only missing value compared to what the real hardware supports. The SoC should support up to 4GB but when setting that the firmware hangs during memory test. This may be an overflow bug in the firmware which I did not try to debug but this may affect real hardware as well. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 22 ++++++++++++---------- hw/ppc/sam460ex.c | 6 ++++-- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 60dbb35eee..414dc19c1d 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -2,7 +2,7 @@ * QEMU PowerPC 440 embedded processors emulation * * Copyright (c) 2012 Fran\ufffd\ufffdois Revol - * Copyright (c) 2016-2018 BALATON Zoltan + * Copyright (c) 2016-2019 BALATON Zoltan * * This work is licensed under the GNU GPL license version 2 or later. * @@ -505,10 +505,6 @@ enum { SDRAM_PLBADDUHB =3D 0x50, }; =20 -/* XXX: TOFIX: some patches have made this code become inconsistent: - * there are type inconsistencies, mixing hwaddr, target_ulong - * and uint32_t - */ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) { uint32_t bcr; @@ -538,11 +534,17 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram= _size) case (1 * GiB): bcr =3D 0xe000; break; + case (2 * GiB): + bcr =3D 0xc000; + break; + case (4 * GiB): + bcr =3D 0x8000; + break; default: error_report("invalid RAM size " TARGET_FMT_plx, ram_size); return 0; } - bcr |=3D ram_base & 0xFF800000; + bcr |=3D ram_base >> 2 & 0xFFE00000; bcr |=3D 1; =20 return bcr; @@ -550,12 +552,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram= _size) =20 static inline hwaddr sdram_base(uint32_t bcr) { - return bcr & 0xFF800000; + return (bcr & 0xFFE00000) << 2; } =20 -static target_ulong sdram_size(uint32_t bcr) +static uint64_t sdram_size(uint32_t bcr) { - target_ulong size; + uint64_t size; int sh; =20 sh =3D 1024 - ((bcr >> 6) & 0x3ff); @@ -575,7 +577,7 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int i, &sdram->ram_memories[i]); object_unparent(OBJECT(&sdram->containers[i])); } - sdram->bcr[i] =3D bcr & 0xFFDEE001; + sdram->bcr[i] =3D bcr & 0xFFE0FFC1; if (enabled && (bcr & 1)) { memory_region_init(&sdram->containers[i], NULL, "sdram-containers", sdram_size(bcr)); diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 7cbd2f54c6..7cc7d205d1 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -76,9 +76,11 @@ #define UART_FREQ 11059200 #define SDRAM_NR_BANKS 4 =20 -/* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */ +/* The SoC could also handle 4 GiB but firmware does not work with that. */ +/* Maybe it overflows a signed 32 bit number somewhere? */ static const ram_addr_t ppc460ex_sdram_bank_sizes[] =3D { - 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 0 + 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, + 32 * MiB, 0 }; =20 struct boot_info { --=20 2.13.7